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SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 1 preliminary version 1.2 SN8P1989 user?s manual preliminary specification version 1.2 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without furt her notice to any products herein to improve reliab ility, function or design. sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its paten t rights nor the rights of others. sonix products are not designed, intended, or authorized for us as co mponents in systems intended, for surgical implant into the body, or other applications intend ed to support or sustain life, or for any other app lication in which the failure of the sonix product could create a situation where personal injury or d eath may occur. should buyer purchase or use sonix p roducts for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subsidiari es, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reason able attorney fees arising out of, directly or indi rectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 2 preliminary version 1.2 amendent history version date description ver v1.0 may. 2009 v1.0 first issue ver v1.1 jan. 2010 v1.1 add programming pin ver v1.2 jan. 2010 modify lqfp part no.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 3 preliminary version 1.2 table of content amendent history............................................ ................................................... ............................ 2 1 1 1 product overview ................................................... ................................................... .............. 8 1.1 features......................................... ................................................... ....................................... 8 1.2 sysyem block.............................................. ................................................... ........................ 9 1.3 pin assignment......................................... ................................................... ......................... 10 1.4 pin descriptions ....................................... ................................................... ........................ 11 1.5 pin circuit diagram............................................ ................................................... ............ 12 2 2 2 central processor unit (cpu)....................... ................................................... ................. 13 2.1 memory map................................................ ................................................... ....................... 13 2.1.1 program memory (rom)............................... ................................................... ............ 13 2.1.1.1 reset vector (0000h)............................. ................................................... ............... 14 2.1.1.2 interrupt vector (0008h) .......................... ................................................... ........ 15 2.1.1.3 look-up table description..................... ................................................... ......... 17 2.1.1.4 jump table description........................ ................................................... ............. 19 2.1.1.5 checksum calculation .......................... ................................................... .......... 22 2.1.2 code option table .................................. ................................................... .................. 23 2.1.3 data memory (ram).................................. ................................................... .................. 24 2.1.4 system register ....................................... ................................................... .................. 25 2.1.4.1 system register table ......................... ................................................... ............. 25 2.1.4.2 system register description ................... ................................................... ...... 25 2.1.4.3 bit definition of system register .............. ................................................... ... 26 2.1.4.4 program flag.................................. ................................................... ...................... 29 2.1.4.5 program counter............................... ................................................... ................. 30 2.1.5 h, l registers ...................................... ................................................... ........................ 32 2.1.5.1 x registers ................................... ................................................... .......................... 33 2.1.6 y, z registers ...................................... ................................................... ......................... 33 2.1.7 r registers......................................... ................................................... .......................... 35 2.2 addressing mode............................................... ................................................... .............. 36 2.2.1 immediate addressing mode........................... ................................................... ...... 36 2.2.2 directly addressing mode............................. ................................................... ....... 36 2.2.3 indirectly addressing mode.......................... ................................................... ...... 36 2.3 stack operation .......................................... ................................................... .................... 37 2.3.1 overview........................................... ................................................... ............................ 37 2.3.2 stack registers...................................... ................................................... .................... 38 2.3.3 stack operation example ............................. ................................................... ......... 39 3 3 3 reset .............................................. ................................................... .............................................. 40
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 4 preliminary version 1.2 3.1 overview......................................... ................................................... .................................... 40 3.2 power on reset .............................................. ................................................... ................... 41 3.3 watchdog reset .............................................. ................................................... ................ 41 3.4 brown out reset.............................................. ................................................... ................ 42 3.4.1 brown out description ............................... ................................................... ........... 42 3.4.2 the system operating voltage decsription.............. ........................................ 43 3.4.3 brown out reset improvement......................... ................................................... ... 43 3.5 external reset .............................................. ................................................... .................. 45 3.6 external reset circuit ............................................ ................................................... .... 45 3.6.1 simply rc reset circuit ............................... ................................................... ..................... 45 3.6.2 diode & rc reset circuit .............................. ................................................... ................... 46 3.6.3 zener diode reset circuit ............................. ................................................... .................... 46 3.6.4 voltage bias reset circuit.............................. ................................................... ................... 47 3.6.5 external reset ic ................................... ................................................... ........................... 47 4 4 4 system clock ....................................... ................................................... ................................... 48 4.1 overview......................................... ................................................... .................................... 48 4.2 clock block diagram ............................................ ................................................... ....... 48 4.3 oscm register ........................................... ................................................... ........................ 48 4.4 system high clock.............................................. ................................................... ............ 49 4.4.1 external high clock................................ ................................................... ............... 49 4.4.1.1 crystal/ceramic............................... ................................................... ................... 51 4.5 system low clock.............................................. ................................................... ............. 51 4.5.1.1 crystal ....................................... ................................................... ............................. 51 4.5.1.2 rc type........................................ ................................................... ................................ 52 5 5 5 system operation mode .............................. ................................................... ...................... 53 5.1 overview......................................... ................................................... .................................... 53 5.2 system mode switching.......................................... ................................................... ...... 54 5.3 wakeup........................................... ................................................... ...................................... 56 5.3.1 overview........................................... ................................................... ............................ 56 5.3.2 wakeup time ........................................ ................................................... ........................ 56 5.3.3 p1w wakeup control register.......................... ................................................... ... 57 6 6 6 interrupt .......................................... ................................................... ........................................ 58 6.1 overview......................................... ................................................... .................................... 58 6.2 inten interrupt enable register........................................... ..................................... 59 6.3 intrq interrupt request register ........................................... .................................. 60 6.4 gie global interrupt operation .......................................... ....................................... 61 6.5 int0 (p0.0) interrupt operation .......................................... ........................................... 63 6.6 int1 (p0.1) interrupt operation .......................................... ........................................... 64
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 5 preliminary version 1.2 6.7 t0 interrupt operation.......................................... ................................................... ....... 65 6.8 tc0 interrupt operation .......................................... ................................................... .... 66 6.9 tc1 interrupt operation .......................................... ................................................... .... 67 6.10 16 bit adc interrupt operation .......................................... ........................................... 68 6.11 multi-interrupt operation .......................................... ................................................. 69 7 7 7 i/o port........................................... ................................................... ............................................. 71 7.1 i/o port mode ............................................... ................................................... ...................... 71 7.2 i/o pull up register ........................................... ................................................... .............. 72 7.3 i/o port data register ........................................... ................................................... ........ 73 7.4 p ort 2 io/lcd s election ................................................... ................................................... .... 74 8 8 8 timers............................................. ................................................... ............................................. 75 8.1 watchdog timer (wdt) .............................................. ................................................... .... 75 8.2 timer 0 (t0) ................................................ ................................................... ........................... 77 8.2.1 overview........................................... ................................................... ............................ 77 8.2.2 t0m mode register.................................... ................................................... ................ 78 8.2.3 t0c counting register ................................ ................................................... ............ 79 8.2.4 t0 timer operation sequence.......................... ................................................... ..... 80 8.3 timer/counter 0 (tc0) ............................................... ................................................... ...... 81 8.3.1 overview........................................... ................................................... ............................ 81 8.3.2 tc0m mode register ................................... ................................................... .............. 82 8.3.3 tc1x8, tc0x8, tc0gn flags ............................... ................................................... ........ 83 8.3.4 tc0c counting register ............................... ................................................... .......... 84 8.3.5 tc0r auto-load register.............................. ................................................... .......... 86 8.3.6 tc0 clock frequency output (buzzer)................. ............................................... 87 8.3.7 tc0 timer operation sequence ......................... ................................................... ... 88 8.4 timer/counter 1 (tc1) ............................................... ................................................... ...... 90 8.4.1 overview........................................... ................................................... ............................ 90 8.4.2 tc1m mode register ................................... ................................................... .............. 91 8.4.3 tc1x8 flag ........................................... ................................................... ......................... 91 8.4.4 tc1c counting register ............................... ................................................... .......... 92 8.4.5 tc1r auto-load register.............................. ................................................... .......... 94 8.4.6 tc1 clock frequency output (buzzer)................. ............................................... 95 8.4.7 tc1 timer operation sequence ......................... ................................................... ... 96 8.5 pwm0 mode ............................................... ................................................... ........................... 98 8.5.1 overview........................................... ................................................... ............................ 98 8.5.2 tc0irq and pwm duty ................................. ................................................... .............. 99 8.5.3 pwm program example................................ ................................................... ............ 99 8.5.4 pwm0 duty changing notice........................... ................................................... .... 100
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 6 preliminary version 1.2 8.6 pwm1 mode ............................................... ................................................... ......................... 101 8.6.1 overview........................................... ................................................... .......................... 101 8.6.2 tc1irq and pwm duty ................................. ................................................... ............ 102 8.6.3 pwm program example................................ ................................................... .......... 102 8.6.4 pwm1 duty changing notice........................... ................................................... .... 103 8.7 bzo t imer ................................................... ................................................... .......................... 104 9 9 9 lcd driver......................................... ................................................... ...................................... 105 9.1 overview......................................... ................................................... .................................. 105 9.2 lcdm1 register ........................................... ................................................... .................... 106 9.3 lcd timing ............................................. ................................................... ............................ 107 9.4 lcd ram location........................................... ................................................... ............... 108 9.5 option register description ........................................ ............................................... 108 1 1 1 0 0 0 regulator, pgia and adc ............................ ................................................... ................ 110 10.1 overview......................................... ................................................... .................................. 110 10.2 analog input .............................................. ................................................... ..................... 110 10.3 v oltage r egulator (reg).............................................. ................................................... .... 112 10.3.1 regm- regulator mode register............................. ................................................... ....... 112 10.4 pgia -p rogrammable g ain i nstrumentation a mplifier ................................................... .. 113 10.4.1 ampm- amplifier mode register .......................... ................................................... .......... 113 10.4.2 ampcks- pgia clock selection ......................... ................................................... .. 114 10.4.3 ampchs-pgia channel selection ........................ .................................................. 115 10.5 16-b it adc................................................ ................................................... ............................ 116 10.5.1 adc16m- adc mode register .............................. ................................................... ......... 116 10.5.2 adcks- adc clock register........................... ................................................... ............... 117 10.5.3 adcdl- adc low-byte data register..................... ................................................... ...... 118 10.5.4 adcdh- adc high-byte data register ..................... ................................................... .... 118 10.5.5 dfm-adc digital filter mode register .................... ................................................... ..... 119 10.5.6 analog setting and application ................................. ................................................... ...... 120 10.5.7 lbtm : low battery detect register.................... ................................................... ........... 121 1 1 1 1 1 1 2 channel analog to digital converter ............... ............................................. 122 11.1 overview......................................... ................................................... .................................. 122 11.2 adc12m register........................................... ................................................... .................. 123 11.3 adr registers.......................................... ................................................... ........................ 124 11.4 adb registers.......................................... ................................................... ........................ 125 11.5 adc converting time ............................................... ................................................... .... 126 11.6 adc routine example............................................ ................................................... ....... 127 11.7 adc circuit ............................................ ................................................... ........................... 128
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 7 preliminary version 1.2 1 1 1 2 2 2 instruction table .................................. ................................................... ........................ 129 1 1 1 3 3 3 electrical characteristic .......................... ................................................... ........... 131 13.1 absolute maximum rating ............................................. ............................................. 131 13.2 electrical characteristic ..................................... ................................................... . 131 1 1 1 4 4 4 package information ................................ ................................................... .................. 134 14.1 lqfp80 ............................................ ................................................... ...................................... 134 1 1 1 5 5 5 marking definition ................................. ................................................... ...................... 135 15.1 introduction ..................................... ................................................... ............................. 135 15.2 marking indetification system ............................................. ................................... 135 15.3 marking example ............................................ ................................................... .............. 136 15.4 d atecode system ................................................... ................................................... .............. 136 1 1 1 6 6 6 programming pin .................................... ................................................... ........................ 137 16.1 writer pin assignment ......................................... ................................................... ....... 137 16.2 programming pin mapping: ........................................... ................................................ 138
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 8 preliminary version 1.2 1 1 1 product overview 1.1 features timer memory configuration seven interrupt sources otp rom size: 12k * 16 bits three internal timer interrupts: t0, tc0, tc1 ram size: 512 * 8 bits (bank 0) two external interrupts: int0, int1 8-levels stack buffer 16-bit adc end of conversion interrupt lcd ram size: 28*4 bits i/o pin configuration single power supply: 4.2v ~5.5v input only: p0 on-chip watchdog timer bi-directional: p1, p2, p5 on- chip regulator with 3.8v voltage output and 10ma driven current. wakeup: p0, p1 on chip regulator with 3.0v/2.4v/1.5v output voltag e pull-up resisters: p0, p1, p2, p5 on- chip 1.2v band gap reference for battery monitor. external interrupt: p0 on chip voltage comparator. build in 16-bit adc reference voltage v(r+,r- )=0.8v /0.64v/0.4v. powerful instructions build in buzzer output (bzo) of 6.25k or 50k. four clocks per instruction cycle lcd driver: all instructions are one word length 1/3 bias voltage. most of instructions are 1 cycle only. 4 common * 28 segment maximum instruction cycle is ?2?. jmp instruction jumps to all rom area. dual clock system offers four operating modes all rom area look-up table function (movc) external high clock: up to 8 mhz normal mode: both high and low clock active. programmable gain instrumentation amplifier slow mode: low clock only. gain option: 1x/12.5x/50x/100x/200x green mode with t0 period wake-up 16-bit delta-sigma adc with 14-bit noise free sleep mode: both high and low clock stop. with one fully differential adc input channel package 12-bit adc with two channel single-ended lqfp 80, dice input and built in battery detect. an 8 - bit basic timer with green mode wakeup function. two 8-bit timer counter with pwm or buzzer on chip watchdog timer real time clock(rtc) with 0.5 second.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 9 preliminary version 1.2 1.2 sysyem block interrupt control external high osc. acc external low osc. timing generator ram system registers lvd (low voltage detector) watchdog timer pgia timer & counter p0 p5 16-bit adc regulator alu pc flags ir otp rom ai+/ai- avddr ave+ r+/r- internal reference p1 p2 lcd driver 4 com * 28 seg com0~com3 seg0~seg27 12-bit adc ain0/ain1
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 10 preliminary version 1.2 1.3 pin assignment vlcd com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v2 1 o 60 seg15 v1 2 59 seg16 r+ 3 58 seg17 r- 4 57 seg18 x+ 5 56 seg19 x- 6 55 vlcd1 ao- 7 54 seg20/p2.0 ao+ 8 53 seg21/p2.1 ai+ 9 52 seg22/p2.2 ai- 10 51 seg23/p2.3 avss 11 SN8P1989 50 vlcd2 acm 12 49 seg24/p2.4 avddr 13 48 seg25/p2.5 ave+ 14 47 seg26/p2.6 ain1 15 46 seg27/p2.7 ain0 16 45 vss avrefh 17 44 bzo vdd 18 43 p5.7 lxin 19 42 p5.6 lxout 20 41 p5.5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 xin xout vss vpp/rst p0.0/int0 p0.1/int1 p1.0 .00 aa p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 vdd p5.0 p5.1 p5.2/lbtin p5.3/pwm1/bz1 /p5.4/pwm0/bz0
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 11 preliminary version 1.2 1.4 pin descriptions pin name type description vdd, vss, avss p power supply input pins for digital / analog circui t. vdd pin function description: pin 38: for digital function and io power. pin 21: for 12-bit adc circuit power pin 17: for regulator/pgia/16-bit adc power. vlcd/vlcd1/vlcd2 p lcd power supply input avddr p regulator power output pin, voltage=3.8v. ave+ p regulator output =3.0v or 1.5v for sensor. m aximum output current=10 ma acm p band gap voltage output =1.2v r+ ai positive reference input r- ai negative reference input x+ ai positive adc differential input, a 0.1uf capa citor connect to pin x- x- ai negative adc differential input ai+/- ai pgia/16 bit adc analog input channel ain0, ain1 i/o 12-bit adc input channel vpp/ rst p, i otp rom programming pin. system reset input pin. schmitt trigger structure, active ?low?, normal stay to ?high?. xin, xout i, o external high clock oscillator pins. lxin, lxout i, o external low clock oscillator pins . p0.0 / int0 i port 0.0 and shared with int0 trigger pin (schmitt trigger) / built-in pull-up resisters . p0.1 / int1 i port 0.1 and shared with int1 trigger pin (schmitt trigger) / built-in pull-up resisters . p1 [7:0] i/o port 1.0~port 1.7 bi-direction pins / wakeup pins/ built-in pull-up resisters. p2 [7:0] i/o port 2.0~port 2.7 bi -direction pins / built-in pull-up resisters. share d with lcd p5 [2:0], p5 [5:7] i/o port 5.0~port 5.2, p5.5~p5. 7, bi-direction pins / built-in pull-up resisters. p5.3 / bz1 / pwm1 i/o port 5.3 bi-direction pin, bu ilt-in pull-up resisters. buzzer1 or pwm1 output pi n. p5.4 / bz0 / pwm0 i/o port 5.4 bi-direction pin, bu ilt-in pull-up resisters. buzzer0 or pwm0 output pi n. lbtin i low battery detect input pin shared with p5 .2 com [3:0] o com0~com3 lcd driver common port seg0 ~ seg27 o lcd driver segment pins. bzo o build in buzzer output of 6.25k to 250k.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 12 preliminary version 1.2 1.5 pin circuit diagram port 0 port 1, port5 port 2 pull-up pin pnur input bus pull-up pin output latch pnm, pnur input bus pnm output bus int. lcd seg p2xseg pull-up output latch pnm, pnur input bus pnm output bus pin
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 13 preliminary version 1.2 2 2 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) 12k words rom rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 2ffbh general purpose area end of user program 2ffch . 2fffh reserved
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 14 preliminary version 1.2 2.1.1.1 reset vector (0000h) a one-word vector address area is used to execute s ystem reset. power on reset watchdog rese external reset after power on reset, external reset or watchdog ti mer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. the following example shows the way to define the reset vector in the program memory. example: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. ? org 10h start: ; 0010h, the head of user program. ? ; user program ? endp ; end of program
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 15 preliminary version 1.2 2.1.1.2 interrupt vector (0008h) a 1-word vector address area is used to execute int errupt request. if any interrupt service executes, the program counter (pc) value is stored in stack buffer and ju mp to 0008h of program memory to execute the vector ed interrupt. users have to define the interrupt vector. the foll owing example shows the way to define the interrupt vector in the program memory. note: ?push?, ?pop? instructions only process 0x80~ 0x87 working registers and pflag register. users have to save and load acc by program as interrupt o ccurrence. example: defining interrupt vector. the interrupt s ervice routine is following org 8. .data accbuf ds 1 ; define accbuf for store acc da ta. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. b0xch a, accbuf ; save acc in a buffer push ; save 0x80~0x87 working registers and pflag regist er to buffers. ? ? pop ; load 0x80~0x87 working registers and pflag regist er from buffers. b0xch a, accbuf ; restore acc from buffer reti ; end of interrupt service routine ? start: ; the head of user program. ? ; user program ? jmp start ; end of user program ? endp ; end of program
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 16 preliminary version 1.2 example: defining interrupt vector. the interrupt s ervice routine is following user program. .data accbuf ds 1 ; define accbuf for store acc da ta. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. jmp my_irq ; 0008h, jump to interrupt service rout ine address. org 10h start: ; 0010h, the head of user program. ? ; user program. ? ? jmp start ; end of user program. ? my_irq: ;the head of interrupt service routine. b0xch a, accbuf ; save acc in a buffer push ; save 0x80~0x87 working registers and pflag regist er to buffers. ? ? pop ; load 0x80~0x87 working registers and pflag regist er from buffers. b0xch a, accbuf ; restore acc from buffer reti ; end of interrupt service routine. ? endp ; end of program. note: it is easy to understand the rules of sonix p rogram from demo programs given above. these points are as following: 1. the address 0000h is a ?jmp? instruction to make the program starts from the beginning. 2. the address 0008h is interrupt vector. 3. user?s program is a loop routine for main purpos e application.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 17 preliminary version 1.2 2.1.1.3 look-up table description in the rom?s data lookup function, x register is po inted to high byte address (bit 16~bit 23), y regis ter is pointed to middle byte address (bit 8~bit 15) and z register i s pointed to low byte address (bit 0~bit 7) of rom. after movc instruction executed, the low-byte data will be sto red in acc and high-byte data stored in r register. example: to look up the rom data located ?table1?. b0mov x, #table1$h ; to set lookup table1?s high a ddress b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low a ddress. movc ; to lookup data, r = 00h, acc = 35h ; increment the index address for next address. incms z ; z+1 jmp @f ; z is not overflow. incms y ; z is overflow, y=y+1. jmp @f ; y is not overflow. incms x ; y is overflow, x=x+1. nop ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? note: the x, y registers will not increase automatically when y, z registers crosses boundary from 0xff to 0x00. therefore, user must take care such situat ion to avoid loop-up table errors. if z register is overflow, y register must be added one. if y regist er is overflow, x register must be added one. the following inc_xyz macro shows a simple method to pr ocess x, y and z registers automatically. example: inc_xyz macro. inc_xyz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 jmp @f ; not overflow incms x ; x+1 nop ; not overflow @@: endm
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 18 preliminary version 1.2 example: modify above example by ?inc_xyz? macro. b0mov x, #table1$h ; to set lookup table1?s high a ddress b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low a ddress. movc ; to lookup data, r = 00h, acc = 35h inc_xyz ; increment the index address for next address. ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? the other example of loop-up table is to add x, y o r z index register by accumulator. please be carefu l if ?carry? happen. example: increase y and z register by b0add/add ins truction. b0mov x, #table1$h ; to set lookup table1?s high address b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table?s low ad dress. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. jmp getdata ; y is not overflow. incms x ; y is overflow, x=x+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x00 35 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 ? table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ?
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 19 preliminary version 1.2 2.1.1.4 jump table description the jump table operation is one of multi-address ju mping function. add low-byte program counter (pcl) and acc value to get one new pcl. the new program counter ( pc) points to a series jump instructions as a listi ng table. it is easy to make a multi-jump program depends on the va lue of the accumulator (a). when carry flag occurs after executing of ?add pcl, a?, it will not affect pch register. users have to check if the jump table leaps over the rom page boundary or the listi ng file generated by sonix assembly software. if th e jump table leaps over the rom page boundary (e.g. from xxffh t o xx00h), move the jump table to the top of next pr ogram memory page (xx00h). here one page mean 256 words. note: program counter can?t carry from pcl to pch when pcl is overflow after executing ad dition instruction. example: jump table. org 0x0100 ; the jump table is from the head of t he rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00 fd. when execute b0add pcl, a. if acc = 0 or 1, the jump table points to the right address. if the acc is larger t hen 1 will cause error because pch doesn't increase one automatically. we can see the pcl = 0 when acc = 2 but the pch sti ll keep in 0. the program counter (pc) will point t o a wrong address 0x0000 and crash system operation. it is im portant to check whether the jump table crosses ove r the boundary (xxffh to xx00h). a good coding style is to put the jump table at the start of rom boundary (e.g. 0100 h). example: if ?jump table? crosses over rom boundary will cause errors. rom address ? ? ? 0x00fd b0add pcl, a ; pcl = pcl + acc, the pch can?t be ch anged. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 jump table cross boundary here 0x0101 jmp a3point ; acc = 3 ? ?
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 20 preliminary version 1.2 sonix provides a macro for safe jump table function . this macro will check the rom boundary and move t he jump table to the right position automatically. the side effect of this macro maybe wastes some rom size. example: if ?jump table? crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm note: ?val? is the number of the jump table listing number. example: ?@jmp_a? application in sonix macro file c alled ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is across a rom boundary (0x00ff~0x0100), the ?@jmp_a? macro will adjust th e jump table routine begin from next ram boundary (0x0100). example: ?@jmp_a? operation. ; before compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x00fd jmp a0point ; acc = 0, jump to a0point 0x00fe jmp a1point ; acc = 1, jump to a1point 0x00ff jmp a2point ; acc = 2, jump to a2point 0x0100 jmp a3point ; acc = 3, jump to a3point 0x0101 jmp a4point ; acc = 4, jump to a4point ; after compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x0100 jmp a0point ; acc = 0, jump to a0point 0x0101 jmp a1point ; acc = 1, jump to a1point 0x0102 jmp a2point ; acc = 2, jump to a2point 0x0103 jmp a3point ; acc = 3, jump to a3point 0x0104 jmp a4point ; acc = 4, jump to a4point
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 21 preliminary version 1.2
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 22 preliminary version 1.2 2.1.1.5 checksum calculation the last rom address are reserved area. user should avoid these addresses (last address) when calculat e the checksum value. example: the demo program shows how to calculated c hecksum from 00h to the end of user?s code. mov a,#end_user_code$l b0mov end_addr1, a ; save low end address to end_a ddr1 mov a,#end_user_code$m b0mov end_addr2, a ; save middle end address to en d_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: movc b0bset fc ; clear c flag add data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end addre ss jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is d one. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: ? ? end_user_code: ; label of program end
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 23 preliminary version 1.2 2.1.2 code option table code option content function description enable enable watchdog function watch_dog disable disable watchdog function enable enable noise filter function noise filter disable disable noise filter function enable enable rom code security function security disable disable rom code security function always_on force watch dog timer clock source come from int 16 k rc. also int 16k rc never stop both in power down and g reen mode that means watch dog timer will always enable both in po wer down and green mode. int_16k_rc by_cpum enable or disable internal 16k(@ 3v) rc clo ck by cpum register enable enable low power function to save operating current low power disable disable low power function note: 1. in high noisy environment, set watch_dog as ?enable ? and int_16k_rc as ?always_on? is strongly recommended. 2. in high noisy environment, disable ?low power? is s trongly recommended. 3. the side effect is to increase the lowest valid wor king voltage level if enable ?low power? code option. 4. enable ?low power? option will reduce operating cur rent except in slow mode.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 24 preliminary version 1.2 2.1.3 data memory (ram) 512 x 8-bit ram ram location 000h general purpose area ; 000h~07fh of bank 0 = t o store general . ; purpose data (128 bytes). 07fh . 080h system register ; 080h~0ffh of bank 0 = to sto re system . ; registers (128 bytes). bank 0 0ffh end of bank 0 area 0100h general purpose area ; 0100h~01ffh of bank 1 = to s tore general . ; purpose data (256 bytes). . . bank1 01ffh end of bank1area 0200h general purpose area ; 0200h~027fh of bank 2 = to s tore general . ; purpose data (128 bytes). bank 2 027fh end of bank 2 area f00h lcd ram area ; bank 15 = to store lcd display data . ; (28 bytes). bank 15 f1ch end of lcd ram ;
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 25 preliminary version 1.2 2.1.4 system register 2.1.4.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y x pflag rbank option lcdm1 - - - - - - 9 ampm ampchs ampcks adc16m adcks regm dfm adcdl adcdh lbtm bzc bzm - - - a - - - - - - - - - - - - - - - - b - adc12m adb adr - - - - - - - - - - - pedge c p1w p1m p2m - - p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 p2 - - p5 - - t0m t0c tc0m tc0c tc1m tc1c tc1r stkp e p0ur p1ur p2ur - - p5ur @hl @yz - - - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.4.2 system register description l, h = working, @hl and rom addressing register x = working register and rom look-up data buffer y, z = working, @yz and rom addressing register r = working register and rom look-up data buffer pflag = rom page and special flag register ampchs = pgia channel selection ampm = pgia mode register adc16m = 16 bit adc?s mode register ampcks = pgia clock selection regm = regulator mode adcks = adc clock selection dfm = decimation filter mode adcdh = adc high-byte data buffer adcdl = adc low-byte data buffer p n ur = port n pull-up register p n m = port n input/output mode register intrq = interrupt request register p n = port n data buffer oscm = oscillator mode register inten = interrupt enable register pch, pcl = program counter lcdm1= lcd mode register stk0~stk7 = stack 0 ~ stack 7 buffer t0m = timer 0 mode register t0c = timer 0 counting register @hl = ram hl indirect addressing index pointer. @yz = ram yz indirect addressing index pointer. stkp = stack pointer buffer lbtm= low battery detect register tc0m = timer/counter 0 mode register. t0c = timer 0 counting register. tc0c = timer/counter 0 counting register. tc1m = timer/counter 1 mode register. tc0r = timer/counter 0 auto-reload data buffer. tc1c = timer/counter 1 counting register. tc1r = timer/counter 1 auto-reload data buffer.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 26 preliminary version 1.2 2.1.4.3 bit definition of system register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w name 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 085h xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w x 086h - - - - - c dc z r/w pflag 087h - - - - rbnks3 rbnks2 rbnks1 rbnks0 r/w rbank 088h - - - - - - - rclk r/w option 089h - - lcdbnk - lcdenb - p2hseg p2lseg r/w lcdm1 090h - bgrenb fds1 fds0 gs2 gs1 gs0 ampenb r/w ampm 091h - - - - adc16chs3 adc16chs2 adc16chs1 adc16chs0 r/w ampchs 092h - - - - - ampcks2 ampcks1 ampcks0 w ampcks 093h - - - - irvs rvs1 rvs0 adc16enb r/w adc16m 094h adcks7 adcks6 adcks5 adcks4 adcks3 adcks2 adcks1 adcks0 w adcks 095h acmenb avddrenb avenb avesel1 avesel0 - - regenb r/w regm 097h - - - wrs0 drdy r/w dfm 098h adcb7 adcb6 adcb5 adcb4 adcb3 adcb2 adcb1 adcb0 r adcdl 099h adcb15 adcb14 adcb13 adcb12 adcb11 adcb10 adcb9 adcb8 r adcdh 09ah - - - - - lbto - lbtenb r/w lbtm 09bh bzc7 bzc6 bzc 5 bzc4 bzc3 bzc2 bzc1 bzc0 w bzc 09ch bzoenb bzorate2 bzorate1 bzorate0 - bzox8 - - r/w bzm 0b1h adc12enb ads eoc gchs - - adc12chs1 adc12chs0 r/w adc12m 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb 0b3h - ad12cks1 - ad12cks0 adb3 adb2 adb1 adb0 r/w adr 0bfh pedgen - - p00g1 p00g0 - - - r/w pedge 0c0h p17w p16w p15w p14w p13w p12w p11w p10w r/w p1w 0c1h p17m p16m p15m p14m p13m p12m p11m p10m r/w p1m 0c2h p27m p26m p25m p24m p23m p22m p21m p20m r/w p2m 0c5h p57m p56m p55m p54m p53m p52m p51m p50m r/w p5m 0c8h - tc1irq tc0irq t0irq - adc16irq p01irq p00irq r/w intrq 0c9h - tc1ien tc0ien t0ien - adc16ien p01ien p00ien r/w inten 0cah wtcks wdrst wdrate cpum1 cpum0 clkmd stphx - r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w t c0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - pc13 pc12 pc11 pc10 pc9 pc8 r/w pch 0d0h - - - - - - p01 p00 r p0 0d1h p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 0d2h p27 p26 p25 p24 p23 p22 p21 p20 r/w p2 0d5h p57 p56 p55 p54 p53 p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 - aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rate1 tc1rate0 - aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w t c1r 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp 0e0h - - - - - - p01r p00r w p0ur 0e1h p17r p16r p15r p14r p13r p12r p11r p10r w p1ur 0e2h p27r p26r p25r p24r p23r p22r p21r p20r w p2ur 0e5h p57r p56r p55r p54r p53r p52r p51r p50r w p5ur 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 27 preliminary version 1.2 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - s7pc13 s7pc12 s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - s6pc13 s6pc12 s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h - - s5pc13 s5pc12 s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h - - s4pc13 s4pc12 s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h - - s3pc13 s3pc12 s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh - - s2pc13 s2pc12 s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - s1pc13 s1pc12 s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - s0pc13 s0pc12 s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h note: 1. to avoid system error, make sure to put all the ?0? and ?1? as it indicates in the above table . 2. all of register names had been declared in sn8as m assembler. 3. one-bit name had been declared in sn8asm assembl er with ?f? prefix code. 4. ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instructions are only available to the ?r/w? registers.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 28 preliminary version 1.2 accumulator the acc is an 8-bit data register responsible for t ransferring or manipulating data between alu and da ta memory. if the result of operating is zero (z) or there is car ry (c or dc) occurrence, then these flags will be s et to pflag register. acc is not in data memory (ram), so acc can?t be ac cess by ?b0mov? instruction during the instant addr essing mode. example: read and write acc value. ; read acc data and store in buf data memory mov buf, a ; write a immediate data into acc mov a, #0fh ; write acc data from buf data memory mov a, buf the system doesn?t store acc and pflag value when i nterrupt executed. acc and pflag data must be saved to other data memories. ?push?, ?pop? save and load 0x 80~0x87 system registers data into buffers. users h ave to save acc data by program. example: protect acc and working registers. .data accbuf ds 1 ; define accbuf for store acc da ta. .code int_service: b0xch a, accbuf ; save acc to buffer. push ; save pflag and working registers to buffer . ? . ? pop ; load pflag and working registers form buffe rs. b0xch a, accbuf ; load acc form buffer. reti ; exit interrupt service vector note: to save and re-load acc data, users must use ?b0xch? instruction, or else the pflag register might be modified by acc operation.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 29 preliminary version 1.2 2.1.4.4 program flag the pflag register contains the arithmetic status o f alu operation, c, dc, z bits indicate the result status of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag - - - - - c dc z read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 bit 2 c: carry flag 1 = addition with carry, subtraction without borrow ing, rotation with shifting out logic ?1?, comparis on result 0. 0 = addition without carry, subtraction with borrow ing signal, rotation with shifting out logic ?0?, c omparison result < 0. bit 1 dc: decimal carry flag 1 = addition with carry from low nibble, subtractio n without borrow from high nibble. 0 = addition without carry from low nibble, subtrac tion with borrow from high nibble. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operat ion is zero. 0 = the result of an arithmetic/logic/branch operat ion is not zero. note: refer to instruction set table for detailed i nformation of c, dc and z flags.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 30 preliminary version 1.2 2.1.4.5 program counter the program counter (pc) is a 13-bit binary counter separated into the high-byte 6 and the low-byte 8 bits. this counter is responsible for pointing a location in o rder to fetch an instruction for kernel circuit. no rmally, the program counter is automatically incremented with each inst ruction during program execution. besides, it can be replaced with specific address b y executing call or jmp instruction. when jmp or ca ll instruction is executed, the destination address will be insert ed to bit 0 ~ bit 10. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl one address skipping there are nine instructions (cmprs, incs, incms, de cs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these i nstructions is true, the pc will add 2 steps to ski p next instruction. if the condition of bit test instruction is true, t he pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. ? ? c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. ? ? c1step: nop if the acc is equal to the immediate data or memory , the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. ? ? c0step: nop
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 31 preliminary version 1.2 if the destination increased by 1, which results ov erflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop if the destination decreased by 1, which results un derflow of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 32 preliminary version 1.2 multi-address jumping users can jump around the multi-address by either j mp instruction or add m, a instruction (m = pcl) to activate multi-address jumping function. program counter sup ports ?add m,a? , ?adc m,a? and ?b0add m,a? instructions for carry to pch when pcl overflow automatically. f or jump table or others applications, users can cal culate pc value by the three instructions and don?t care pcl overfl ow problem. note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ? ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point ? ? 2.1.5 h, l registers the h and l registers are the 8-bit buffers. there are two major functions of these registers. can be used as general working registers can be used as ram data pointers with @hl register 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset x x x x x x x x 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset x x x x x x x x example: if want to read a data from ram address 20 h of bank_0, it can use indirectly addressing mode to
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 33 preliminary version 1.2 access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc example: clear general-purpose data memory area of bank 0 using @hl register. clr h ; h = 0, bank 0 b0mov l, #07fh ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l ? 1, if l = 0, finish the routine jmp clr_hl_buf ; not zero clr @hl end_clr: ; end of clear general purpose data memo ry area of bank 0 ? ? 2.1.5.1 x registers x register is an 8-bit buffer. there are two major functions of the register. can be used as general working registers can be used as rom data pointer with the movc inst ruction for look-up table 085h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note: please refer to the ?look-up table descriptio n? about x register look-up table application. 2.1.6 y, z registers the y and z registers are the 8-bit buffers. there are three major functions of these registers. can be used as general working registers can be used as ram data pointers with @yz register can be used as rom data pointer with the movc inst ruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - -
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 34 preliminary version 1.2 example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memo ry area of bank 0 ?
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 35 preliminary version 1.2 2.1.7 r registers r register is an 8-bit buffer. there are two major functions of the register. can be used as working register for store high-byte data of look-up table (movc instruction executed, the high-byte data of s pecified rom address will be stored in r register a nd the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - note: please refer to the ?look-up table descriptio n? about r register look-up table application.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 36 preliminary version 1.2 2.2 addressing mode 2.2.1 immediate addressing mode the immediate addressing mode uses an immediate dat a to set up the location in acc or specific ram. example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into ac c. example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. note: in immediate addressing mode application, the specific ram must be 0x80~0x87 working register. 2.2.2 directly addressing mode the directly addressing mode moves the content of r am location in or out of acc. example: move 0x12 ram location data into acc. b0mov a, 12h ; to get a content of ram location 0x12 of bank 0 a nd save in acc. example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.2.3 indirectly addressing mode the indirectly addressing mode is to access the mem ory by the data pointer registers (h/l, y/z). example: indirectly addressing mode with @hl regist er b0mov h, #0 ; to clear h register to access ram ba nk 0. b0mov l, #12h ; to set an immediate data 12h into l register. b0mov a, @hl ; use data pointer @hl reads a data f rom ram location ; 012h into acc. example: indirectly addressing mode with @yz regist er b0mov y, #0 ; to clear y register to access ram ba nk 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data f rom ram location ; 012h into acc.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 37 preliminary version 1.2 2.3 stack operation 2.3.1 overview the stack buffer has 8-level. these buffers are des igned to push and pop up program counter?s (pc) dat a when interrupt service routine and ?call? instruction ar e executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack bu ffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 38 preliminary version 1.2 2.3.2 stack registers the stack pointer (stkp) is a 3-bit register to sto re the address used to access the stack buffer, 11- bit data memory (stknh and stknl) set aside for temporary storage o f stack addresses. the two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always p oint to the top address of stack buffer and write the last program counter value (pc) into the stack buffer. the program counter (pc) value is stored in the sta ck buffer before a call instruction executed or dur ing interrupt service routine. stack operation is a lifo type (la st in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in the system registe r area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit[2:0] stkpbn: stack pointer (n = 0 ~ 2) bit 7 gie: global interrupt control bit. 0 = disable. 1 = enable. please refer to the interrupt chapter. example: stack pointer (stkp) reset, we strongly re commended to clear the stack pointer in the beginning of the program. mov a, #00000111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - snpc13 snpc12 snpc11 snpc10 snpc9 snpc8 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 39 preliminary version 1.2 2.3.3 stack operation example the two kinds of stack-save operations refer to the stack pointer (stkp) and write the content of prog ram counter (pc) to the stack buffer are call instruction and interr upt service. under each condition, the stkp decreas es and points to the next available stack location. the stack buffer stores the program counter about the op-code addre ss. the stack-save operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack-restore operations correspond to ea ch push operation to restore the program counter (p c). the reti instruction uses for interrupt service routine. the ret instruction is for call instruction. when a po p operation occurs, the stkp is incremented and points to the next free stack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack-re store operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 40 preliminary version 1.2 3 3 3 reset 3.1 overview the system would be reset in three conditions as fo llowing. power on reset watchdog reset brown out reset external reset when any reset condition occurs, all system registe rs keep initial status, program stops and program c ounter is cleared. after reset status released, the system boots up an d program starts to execute from org 0. finishing any reset sequence needs some time. the s ystem provides complete procedures to make the powe r on reset successful. for different oscillator types, the res et time is different. that causes the vdd rise rate and start-up time of different oscillator is not fixed. rc type oscillat or?s start-up time is very short, but the crystal t ype is longer. under client terminal application, users have to take care the p ower on reset time for the master terminal requirem ent. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 41 preliminary version 1.2 3.2 power on reset the power on reset depend no lvd operation for most power-up situations. the power supplying to system is a rising curve and needs some time to achieve the normal vol tage. power on reset sequence is as following. power-up: system detects the power voltage up and waits for power stable. external reset: system checks external reset pin status. if extern al reset pin is not high level, the system keeps reset status and waits external reset pin released. system initialization: all system registers is set as initial conditions and system is ready. oscillator warm up: oscillator operation is successfully and supply to system clock. program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal co ndition, system works well and clears watchdog time r by program. under error condition, system is in unknown situati on and watchdog can?t be clear by program before wa tchdog timer overflow. watchdog timer overflow occurs and the sy stem is reset. after watchdog reset, the system res tarts and returns normal mode. watchdog reset sequence is as following. watchdog timer status: system checks watchdog timer overflow status. if w atchdog timer overflow occurs, the system is reset. system initialization: all system registers is set as initial conditions and system is ready. oscillator warm up: oscillator operation is successfully and supply to system clock. program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. before clearing watchdog timer, check i/o status a nd check ram contents can improve system error. don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main r outine fail. clearing watchdog timer program is only at one par t of the program. this way is the best structure to enhance the watchdog timer function. note: please refer to the ?watchdog timer? about wa tchdog timer detail information.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 42 preliminary version 1.2 3.4 brown out reset 3.4.1 brown out description the brown out reset is a power dropping condition. the power drops from normal voltage to low voltage by external factors (e.g. eft interference or external loading changed). the brown out reset would make the system not work well or executing program error. vdd vss v1 v2 v3 system work well area system work error area brown out reset diagram the power dropping might through the voltage range that?s the system dead-band. the dead-band means th e power range can?t offer the system minimum operation powe r requirement. the above diagram is a typical brown out reset diagram. there is a serious noise under the vdd, an d vdd voltage drops very deep. there is a dotted li ne to separate the system working area. the above area is the syst em work well area. the below area is the system wor k error area called dead-band. v1 doesn?t touch the below area a nd not effect the system operation. but the v2 and v3 is under the below area and may induce the system error occurren ce. let system under dead-band includes some condit ions. dc application: the power source of dc application is usually using battery. when low battery condition and mcu drive any loading, the power drops and keeps in dead-band. under the s ituation, the power won?t drop deeper and not touch the system reset voltage. that makes the system under dead-ban d. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually co uples with ac noise that makes the dc power dirty. or the externa l loading is very heavy, e.g. driving motor. the lo ading operating induces noise and overlaps with the dc power. vdd d rops by the noise, and the system works under unsta ble power situation. the power on duration and power down duration are l onger in ac application. the system power on sequen ce protects the power on successful, but the power down situati on is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead-band for a while.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 43 preliminary version 1.2 3.4.2 the system operating voltage decsription to improve the brown out reset needs to know the sy stem minimum operating voltage which is depend on t he system executing rate and power level. different system ex ecuting rates have different system minimum operati ng voltage. the electrical characteristic section shows the sys tem voltage to executing rate relationship. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area normally the system operation voltage area is highe r than the system reset voltage to vdd, and the res et voltage is decided by lvd detect level. the system minimum ope rating voltage rises when the system executing rate upper even higher than system reset voltage. the dead-band def inition is the system minimum operating voltage abo ve the system reset voltage. 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset a s following. lvd reset watchdog reset reduce the system executing rate external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) note: 1. the ? zener diode reset circuit?, ?voltage bias reset circuit? and ?external reset ic? can completely improve the brown out reset, dc low batt ery and ac slow power down conditions. 2. for ac power application and enhance eft perform ance, the system clock is 4mhz/4 (1 mips) and use external reset (? zener diode reset circuit ?, ?voltage bias reset circuit?, ?external reset ic?). the structure can improve noise effective and get good eft characteristic.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 44 preliminary version 1.2 lvd reset: vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset. the lvd (low voltage detector) is built-in sonix 8- bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be trigg ered, and the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volta ge and not easy to cover all dead-band range. using lvd to improve brown out reset is depend on application re quirement and environment. if the power variation i s very deep, violent and trigger the lvd, the lvd can be the pro tection. if the power variation can touch the lvd d etect level and make system work error, the lvd can?t be the protec tion and need to other reset methods. more detail l vd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog t imer in several addresses. the system executes norm ally and the watchdog won?t reset system. when the system is und er dead-band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously c ounting until overflow occurrence. the overflow sig nal of watchdog timer triggers the system to reset, and th e system return to normal mode after reset sequence . this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is st ill in dead-band, the system reset sequence won?t b e successful and the system stays in reset status until the powe r return to normal range. reduce the system executing rate: if the system rate is fast and the dead-band exists , to reduce the system executing rate can improve t he dead-band. the lower system rate is with lower minimum operati ng voltage. select the power voltage that?s no dead -band issue and find out the mapping system rate. adjust the sy stem rate to the value and the system exits the dea d-band issue. this way needs to modify whole program timing to fi t the application requirement. external reset circuit: the external reset methods also can improve brown o ut reset and is the complete solution. there are th ree external reset circuits to improve brown out reset including ?zener diode reset circuit?, ?voltage bias reset c ircuit? and ?external reset ic?. these three reset structures use externa l reset signal and control to make sure the mcu be reset under power dropping and under dead-band. the external re set information is described in the next section.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 45 preliminary version 1.2 3.5 external reset external reset pin is schmitt trigger structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low volta ge and the system is reset. the external reset oper ation actives in power on and normal running mode. during system pow er-up, the external reset pin must be high level in put, or the system keeps in reset status. external reset sequen ce is as following. external reset: system checks external reset pin status. if extern al reset pin is not high level, the system keeps reset status and waits external reset pin released. system initialization: all system registers is set as initial conditions and system is ready. oscillator warm up: oscillator operation is successfully and supply to system clock. program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during powe r on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application? 3.6 external reset circuit 3.6.1 simply rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow ri sing signal into reset pin as power up. the reset signal is slower t han vdd power up timing, and system occurs a power on signal from the timing difference. note: the reset circuit is no any protection agains t unusual power or brown out reset.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 46 preliminary version 1.2 3.6.2 diode & rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm this is the better reset circuit. the r1 and c1 cir cuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against u nusual power. the diode offers a power positive pat h to conduct higher power to vdd. it is can make reset pin volta ge level to synchronize with vdd voltage. the struc ture can improve slight brown out reset condition. note: the r2 100 ohm resistor of ?simply reset circ uit? and ?diode & rc reset circuit? is necessary to limit any current flowing into reset pin from exter nal capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or e lectrical over-stress (eos). 3.6.3 zener diode reset circuit mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b the zener diode reset circuit is a simple low volta ge detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vd d voltage level is above ?vz + 0.7v?, the c termina l of the pnp transistor outputs high voltage and mcu ope rates normally. when vdd is below ?vz + 0.7v?, the c terminal of the pnp transistor outputs low voltage and mcu is i n reset mode. decide the reset detect voltage by ze ner specification. select the right zener voltage to co nform the application.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 47 preliminary version 1.2 3.6.4 voltage bias reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b the voltage bias reset circuit is a low cost voltag e detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diod e reset circuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to ?0.7v x (r1 + r2) / r1?, the c terminal of the pnp transistor o utputs high voltage and mcu operates normally. when vdd is belo w ?0.7v x (r1 + r2) / r1?, the c terminal of the pn p transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistanc es. select the right r1, r2 value to conform the ap plication. in the circuit diagram condition, the mcu?s reset pin leve l varies with vdd voltage variation, and the differ ential voltage is 0.7v. if the vdd drops and the voltage lower than r eset pin detect level, the system would be reset. i f want to make the reset active earlier, set the r2 > r1 and the cap b etween vdd and c terminal voltage is larger than 0. 7v. the external reset circuit is with a stable current through r1 a nd r2. for power consumption issue application, e.g . dc power system, the current must be considered to whole sys tem power consumption. note: under unstable power condition as brown out reset, ?zener diode rest circuit? and ?voltage bias reset circuit? can protects system no any error occ urrence as power droppi ng. when power drops below the reset detect voltage, the system reset wo uld be triggered, and then system executes reset sequence. that makes sure the system work wel l under unstable power situation. 3.6.5 external reset ic mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 48 preliminary version 1.2 4 4 4 system clock 4.1 overview the micro-controller is a single clock system. the high-speed clock is generated from the external osc illator circuit. the high-speed clock can be system clock (fosc). the sy stem clock is divided by 4 to be the instruction cy cle (fcpu). normal mode (high clock): fcpu = fhosc/4. slow mode (low clock): fcpu = flosc/4. 4.2 clock block diagram fhosc. fcpu = fhosc/4 flosc. fcpu = flosc/4 cpum[1:0] xin xout stphx hosc fcpu code option fosc fosc clkmd fcpu hosc: high_clk code option. fhosc: external high-speed clock. flosc: external low-speed clock. fosc: system clock source. fcpu: instruction cycle. 4.3 oscm register the oscm register is an oscillator control register . it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx 0 read/write r/w r/w r/w r/w r/w r/w r/w - after reset 0 0 0 0 0 0 0 - bit 1 stphx: external high-speed oscillator control bit. 0 = external high-speed oscillator free run.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 49 preliminary version 1.2 1 = external high-speed oscillator free run stop. e xternal low-speed rc oscillator is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = normal (dual) mode. system clock is high clock. 1 = slow mode. system clock is external low clock. bit[4:3] cpum[1:0]: cpu operating mode control bits. 00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved. bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapte r.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v example: stop high-speed oscillator b0bset fstphx ; to stop external high-speed oscill ator only. example: when entering the power down mode (sleep m ode), both high-speed oscillator and external low-speed oscillator will be stopped. b0bset fcpum0 ; to stop external high-speed oscill ator and external low-speed ; oscillator called power down mode (sleep mode) . 4.4 system high clock 4.4.1 external high clock external high clock includes crystal/ceramic module s .. the start up time of is longer. the oscillator start-up time
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 50 preliminary version 1.2 decides reset time length. 4mhz ceramic 4mhz crystal
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 51 preliminary version 1.2 4.4.1.1 crystal/ceramic crystal/ceramic devices are driven by xin, xout pin s. for high/normal/low frequency, the driving curre nts are different. high_clk code option supports different frequencies. 12m option is for high speed (ex. 12mh z). 4m option is for normal speed (ex. 4mhz). 32k option is for low speed (ex. 32768hz). mcu vcc gnd c 20pf xin x o u t vdd vss c 20pf crystal note: connect the crystal/ceramic and c as near as possible to the xin/xout/vss pins of micro-controller. 4.5 system low clock the system low clock source is the external low-spe ed oscillator. the low-speed oscillator can use 327 68 crystal or rc type oscillator circuit. 4.5.1.1 crystal crystal devices are driven by lxin, lxout pins. the 32768 crystal and 10pf capacitor must be as near a s possible to mcu. mcu vcc gnd c 10pf lxin l x o u t vdd vss c 10pf 32768hz
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 52 preliminary version 1.2 4.5.1.2 rc type the external low clock supports watchdog clock sour ce and system slow mode controlled by clkmd. flosc = external low oscillator slow mode fcpu = flosc / 4 in power down mode the external low clock will be s top. example: stop internal low-speed oscillator by powe r down mode. b0bset fcpum0 ; to stop external high-speed oscill ator and internal low-speed ; oscillator called power down mode (sleep mode) . note: the external low- speed clock can?t be turned off individually. it is controlled by cpum0, cpum1 bits of oscm register. mcu vcc gnd lxin l x o u t v d d vss c 22pf (3v) 35pf (5v)
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 53 preliminary version 1.2 5 5 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around four different modes as following. normal mode (high-speed mode) slow mode (low-speed mode) power-down mode (sleep mode) green mode power down mode (sleep mode) slow mode green mode normal mode clkmd = 1 clkmd = 0 p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01. cpum1, cpum0 = 10. p0, p1 wake-up function active. t0 timer time out. external reset circuit active. p0, p1 wake-up function active. t0 timer time out. external reset circuit active. system mode switching diagram operating mode description mode normal slow green power down (sleep) remark ehosc running by stphx by stphx stop ext. lrc running running running stop cpu instruction executing executing stop stop t0 timer *active *active *active inactive * active if t0enb=1 tc0 timer *active *active *active inactive * active if tc0enb=1 tc1 timer *active *active inactive inactive * activ e if tc1enb=1 watchdog timer by watch_dog code option by watch_dog code option by watch_dog code option by watch_dog code option refer to code option description internal interrupt all active all active t0, tc0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0, tc0 reset p0, p1, reset ehosc : external high clock ext. lrc : external low clock
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 54 preliminary version 1.2 5.2 system mode switching example: switch normal/slow mode to power down (sle ep) mode. b0bset fcpum0 ; set cpum0 = 1. note: during the sleep, only the wakeup pin and res et can wakeup the system back to the normal mode. example: switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high-speed oscilla tor for power saving. example: switch slow mode to normal mode (the exter nal high-speed oscillator is still running) b0bclr fclkmd ;to set clkmd = 0 example: switch slow mode to normal mode (the exter nal high-speed oscillator stops) if external high clock stop and program want to swi tch back normal mode. it is necessary to delay at l east 20ms for external clock stable. b0bclr fstphx ; turn on the external high-speed os cillator. b0mov z, #54 ; if vdd = 5v, internal rc=32khz (typ ical) will delay @@: decms z ; 0.125ms x 162 = 20.25ms for external clock stable jmp @b b0bclr fclkmd ; change the system back to the norm al mode example: switch normal/slow mode to green mode. b0bset fcpum1 ; set cpum1 = 1. note: if t0/tc0 timer wakeup function is disabled i n the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operati on mode.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 55 preliminary version 1.2 example: switch normal/slow mode to green mode and enable t0 wakeup function. ; set t0 timer wakeup function. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial value = 74h (to s et t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 note: during the green mode with t0 wake-up functio n, the wakeup pins, reset pin and t0 can wakeup the system back to the last mode. t0 wake-up period is controlled by program and t0enb must be set.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 56 preliminary version 1.2 5.3 wakeup 5.3.1 overview under power down mode (sleep mode) , program doesn? t execute. the wakeup trigger can wake the system u p to normal mode. the wakeup trigger sources are externa l trigger (p0, p1 level change) power down mode is waked up to normal mode. the wa keup trigger is only external trigger (p0, p1 level change) 5.3.2 wakeup time when the system is in power down mode (sleep mode), the high clock oscillator stops. when waked up fro m power down mode, mcu waits for 2048 external high-speed o scillator clocks as the wakeup time to stable the o scillator circuit. after the wakeup time, the system goes into the nor mal mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + high cloc k start-up time note: the high clock start-up time is depended on t he vdd and oscillator type of high clock. example: in power down mode (sleep mode), the syste m is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the fo llowing. the wakeup time = 1/fosc * 2048 = 0.512 ms (fosc = 4mhz) the total wakeup time = 0.512 ms + oscillator start -up time
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 57 preliminary version 1.2 5.3.3 p1w wakeup control register under power down mode (sleep mode) and green mode, the i/o ports with wakeup function are able to wake the system up to normal mode. the port 0 and port 1 hav e wakeup function. port 0 wakeup function always en ables, but the port 1 is controlled by the p1w register. 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w p17w p16w p15w p14w p13w p12w p11w p10w read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit[7:0] p10w~p17w: port 1 wakeup function control bits. 0 = disable p1n wakeup function. 1 = enable p1n wakeup function.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 58 preliminary version 1.2 6 6 6 interrupt 6.1 overview this mcu provides eight interrupt sources, includin g four internal interrupt (t0/tc0/tc1/16bit adc) an d two external interrupt (int0/int1). the external interrupt can w akeup the chip while the system is switched from po wer down mode to high-speed normal mode, and interrupt request is latched until return to normal mode. once interrup t service is executed, the gie bit in stkp register will clear t o ?0? for stopping other interrupt request. on the contrast, when interrupt service exits, the gie bit will set to ?1 ? to accept the next interrupts? request. all of th e interrupt request signals are stored in intrq register. inten interrupt enable register interrupt enable gating intrq 8-bit latchs p00irq tc0irq tc1irq interrupt vector address (0008h) global interrupt request signal int0 trigger t0 time out tc0 time out tc1 time out int1 trigger p01irq 16-bit adc converting end t0irq adc16irq note: the gie bit must enable during all interrupt operation.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 59 preliminary version 1.2 6.2 inten interrupt enable register inten is the interrupt request control register inc luding three internal interrupts, two external inte rrupts enable control bits. one of the register to be set ?1? is to enabl e the interrupt request function. once of the inter rupt occur, the stack is incremented and program jump to org 8 to execute in terrupt service routines. the program exits the int errupt service routine when the returning interrupt service routin e instruction (reti) is executed. 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten - tc1ien tc0ien t0ien - adc16ien p01ien p00ien read/write - r/w r/w r/w - r/w r/w r/w after reset - 0 0 0 - 0 0 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = disable int0 interrupt function. 1 = enable int0 interrupt function. bit 1 p01ien: external p0.1 interrupt (int1) control bit. 0 = disable int1 interrupt function. 1 = enable int1 interrupt function. bit 2 adc16ien: 16bit adc converting end interrupt control bit. 0 = disable 16bit adc interrupt function. 1 = enable16bit adc interrupt function. bit 4 t0ien: t0 timer interrupt control bit. 0 = disable t0 interrupt function. 1 = enable t0 interrupt function. bit 5 tc0ien: tc0 timer interrupt control bit. 0 = disable tc0 interrupt function. 1 = enable tc0 interrupt function. bit 6 tc1ien: tc1 timer interrupt control bit. 0 = disable tc1 interrupt function. 1 = enable tc1 interrupt function.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 60 preliminary version 1.2 6.3 intrq interrupt request register intrq is the interrupt request flag register. the r egister includes all interrupt request indication f lags. each one of the interrupt requests occurs, the bit of the intrq reg ister would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interr upt vector of program, users know the any interrupt requests occurring by the register and do the routine corres ponding of the interrupt request. 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq - tc1irq tc0irq t0irq - adc16irq p01irq p00irq read/write - r/w r/w r/w - r/w r/w r/w after reset - 0 0 0 - 0 0 0 bit 0 p00irq: external p0.0 interrupt (int0) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 1 p01irq: external p0.1 interrupt (int1) request flag. 0 = none int1 interrupt request. 1 = int1 interrupt request. bit 2 adc16irq: 16bit adc converting end interrupt request flag. 0 = none 16bit adc interrupt request. 1 = 16bit adc interrupt request. bit 4 t0irq: t0 timer interrupt request flag. 0 = none t0 interrupt request. 1 = t0 interrupt request. bit 5 tc0irq: tc0 timer interrupt request flag. 0 = none tc0 interrupt request. 1 = tc0 interrupt request. bit 6 tc1irq: tc1 timer interrupt request flag. 0 = none tc1 interrupt request. 1 = tc1 interrupt request.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 61 preliminary version 1.2 6.4 gie global interrupt operation gie is the global interrupt control bit. all interr upts start work after the gie = 1 it is necessary f or interrupt service request. one of the interrupt requests occurs, and the program counter (pc) points to the interrupt ve ctor (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global interrupt. 1 = enable global interrupt. ? example: set global interrupt control bit (gie). b0bset fgie ; enable gie note: the gie bit must enable during all interrupt operation.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 62 preliminary version 1.2 push, pop routine when any interrupt occurs, system will jump to org 8 and execute interrupt service routine. it is nece ssary to save acc, pflag data. the chip includes ?push?, ?pop? fo r in/out interrupt service routine. the two instruc tion only save working registers 0x80~0x87 including pflag data into buffers. the acc data must be saved by p rogram. note: 1. ?push?, ?pop? instructions only process 0x80~0x87 w orking registers and pflag register. users have to save and load acc by program as interrupt o ccurrence. 2. the buffer of push/pop instruction is only one leve l and is independent to ram or stack area. ? example: store acc and paflg data by push, pop inst ructions when interrupt service routine executed. .data accbuf ds 1 ; accbuf is acc data buffer. .code org 0 jmp start org 8 jmp int_service org 10h start: ? int_service: b0xch a, accbuf ; save acc in a buffer push ; save 0x80~0x87 working registers and pflag regist er to buffers. ? ? pop ; load 0x80~0x87 working registers and pflag regist er from buffers. b0xch a, accbuf ; restore acc from buffer reti ; exit interrupt service vector ? endp
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 63 preliminary version 1.2 6.5 int0 (p0.0) interrupt operation when the int0 trigger occurs, the p00irq will be se t to ?1? no matter the p00ien is enable or disable. if the p00ien = 1 and the trigger event p00irq is also set to be ?1 ?. as the result, the system will execute the inte rrupt vector (org 8). if the p00ien = 0 and the trigger event p00irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the p00irq is set to be ?1?. user s need to be cautious with the operation under mult i-interrupt situation. note: the interrupt trigger direction of p0.0 is co ntrol by pedge register. 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge i nterrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: both wakeup and interrupt trigger are contro lled by p00g1 and p00g0 bits. p0.1: wakeup trigger and interrupt trigger is leve l change (falling or rising edge). port 1: wakeup trigger is level change (falling or rising edge). bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = falling edge, 10 = rising edge, 11 = rising/falling bi-direction. example: setup int0 interrupt request and bi-direct ion edge trigger. mov a, #98h b0mov pedge, a ; set int0 interrupt trigger as bi- direction edge. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq ? ; int0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 64 preliminary version 1.2 6.6 int1 (p0.1) interrupt operation when the int1 trigger occurs, the p01irq will be se t to ?1? no matter the p01ien is enable or disable. if the p01ien = 1 and the trigger event p01irq is also set to be ?1 ?. as the result, the system will execute the inte rrupt vector (org 8). if the p01ien = 0 and the trigger event p01irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the p01irq is set to be ?1?. user s need to be cautious with the operation under mult i-interrupt situation. note: the interrupt trigger direction of p0.1 is co ntrolled by pedgen bit. example: int1 interrupt request setup. b0bset fp01ien ; enable int1 interrupt service b0bclr fp01irq ; clear int1 interrupt request flag b0bset fgie ; enable gie example: int1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 fp01irq ; check p01irq jmp exit_int ; p01irq = 0, exit interrupt vector b0bclr fp01irq ; reset p01irq ? ; int1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 65 preliminary version 1.2 6.7 t0 interrupt operation when the t0c counter occurs overflow, the t0irq wil l be set to ?1? however the t0ien is enable or disa ble. if the t0ien = 1, the trigger event will make the t0irq to be ?1? and the system enter interrupt vector. if t he t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. ? ; t0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 66 preliminary version 1.2 6.8 tc0 interrupt operation when the tc0c counter overflows, the tc0irq will be set to ?1? no matter the tc0ien is enable or disab le. if the tc0ien and the trigger event tc0irq is set to be ?1 ?. as the result, the system will execute the inte rrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set t o be ?1?. moreover, the system won?t execute inter rupt vector even when the tc0ien is set to be ?1?. users need to be cautious with the operation under multi-interrupt s ituation. example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. ? ; tc0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 67 preliminary version 1.2 6.9 tc1 interrupt operation when the tc1c counter overflows, the tc1irq will be set to ?1? no matter the tc1ien is enable or disab le. if the tc1ien and the trigger event tc1irq is set to be ?1 ?. as the result, the system will execute the inte rrupt vector. if the tc1ien = 0, the trigger event tc1irq is still set t o be ?1?. moreover, the system won?t execute inter rupt vector even when the tc1ien is set to be ?1?. users need to be cautious with the operation under multi-interrupt s ituation. example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ftc1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. ? ; tc1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 68 preliminary version 1.2 6.10 16 bit adc interrupt operation when the 16 bit adc converting successfully, the ad c16irq will be set to ?1? no matter the adc16ien is enable or disable. if the adc16ien and the trigger event adc1 6irq is set to be ?1?. as the result, the system w ill execute the interrupt vector. if the adc16ien = 0, the trigger event adc16irq is still set to be ?1?. moreover, t he system won?t execute interrupt vector even when the adc16ien is set to be ?1?. users need to be cautious with the o peration under multi-interrupt situation. example: adc interrupt request setup. b0bclr fadc16ien ; disable adc interrupt service b0bset fadc16ien ; enable adc interrupt service b0bclr fadc16irq ; clear adc interrupt request fla g b0bset fgie ; enable gie b0bset fad16enb ; start adc transformation example: adc interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 fadc16irq ; check 16 bit adcirq jmp exit_int ; adcirq = 0, exit interrupt vector b0bclr fadc16irq ; reset 16 bit adcirq ? ; adc interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 69 preliminary version 1.2 6.11 multi-interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi -interrupt request requires setting the priority of the interr upt requests. the irq flags of interrupts are contr olled by the interrupt event. nevertheless, the irq flag ?1? doesn?t mean the system will execute the interrupt vector. in ad dition, which means the irq flags can be set ?1? by the events wi thout enable the interrupt. once the event occurs, the irq will be logic ?1?. the irq and its trigger event relationsh ip is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge p01irq p0.1 trigger controlled by pedge adc16irq 16-bit adc converting end. t0irq t0c overflow tc0irq tc0c overflow tc1irq tc1c overflow for multi-interrupt conditions, two things need to be taking care of. one is to set the priority for t hese interrupt requests. two is using ien and irq flags to decide which inte rrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 70 preliminary version 1.2 example: check the interrupt request under multi-in terrupt operation org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intp01chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intp01chk: ; check int1 interrupt request b0bts1 fp01ien ; check p01ien jmp intp01chk ; jump check to next interrupt b0bts0 fp01irq ; check p01irq jmp intp01 intdadcchk: ; check 16-bit adc interrupt request b0bts1 fadc16ien ; check dadcien jmp intt0chk ; jump check to next interrupt b0bts0 fadc16irq ; check dadcirq jmp intadc16 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp inttc1chk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine inttc1chk: ; check t1 interrupt request b0bts1 ftc1ien ; check tc1ien jmp intsadchk ; jump check to next interrupt b0bts0 ftc1irq ; check tc1irq jmp intt1 ; jump to tc1 interrupt service routine int_exit: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 71 preliminary version 1.2 7 7 7 i/o port 7.1 i/o port mode the port direction is programmed by pnm register. a ll i/o ports can select input or output direction. 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m p17m p16m p15m p14m p13m p12m p11m p10m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m p27m p26m p25m p24m p23m p22m p21m p20m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m p57m p56m p55m p54m p53m p522m p51m p50m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~5). 0 = pn is input mode. 1 = pn is output mode. note: 1. users can program them by bit control instructio ns (b0bset, b0bclr). 2. port 2 is shared with lcd example: i/o mode selecting clr p1m ; set all ports to be input mode. clr p2m mov a, #0ffh ; set all ports to be output mode. b0mov p1m,a b0mov p2m, a b0bclr p1m.0 ; set p1.0 to be input mode. b0bset p1m.0 ; set p1.0 to be output mode.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 72 preliminary version 1.2 7.2 i/o pull up register 0e0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0ur - - - - - - p01r p00r read/write - - - - - - w w after reset - - - - - - 0 0 0e1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ur p17r p16r p15r p14r p13r p12r p11r p10r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2ur p27r p26r p25r p24r p23r p22r p21r p20r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5ur p57r p56r p55r p54r p53r p52r p51r p50r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 example: i/o pull up register mov a, #0ffh ; enable port0, 1 pull-up register, b0mov p0ur, a ; b0mov p1ur,a
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 73 preliminary version 1.2 7.3 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - - p01 p00 read/write - - - - - - r/w r/w after reset - - - - - - 0 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 p57 p56 p55 p54 p53 p52 p51 p50 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - 0 0 0 example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 4 example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p1, a b0mov p5, a example: write one bit data to output port. b0bset p1.0 ; set p1.0 to be ?1?. b0bclr p1.0 ; set p1.0 to be ?0?.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 74 preliminary version 1.2 7.4 port 2 io/lcd selection the port 2 is shared with lcd and can be set as io pin by pin 089h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcdm1 - - lcdbnk - lcdenb - p2hseg p2lseg r/w - - r/w - r/w - r/w r/w after reset - - 0 - 0 - 0 0 bit5 lcdbnk: lcd blank control bit. 0 = normal display 1 = all of the lcd dots off. bit3 lcdenb: lcd driver enable control bit. 0 = disable lcd function 1 = enable lcd function bit1 p2hseg : seg20~23 lcd/io selection bit. 0 = seg20~23 as lcd function. vlcd1 connect to vlcd 1 = seg20~23 as io function (p2.0~p2.3). vlcd1 conne ct to vdd bit0 p2lseg : seg24~27 lcd/io selection bit. 0 = seg24~27 as lcd function. vlcd2 connect to vlcd 1 = seg24~27 as io function (p2.4~p2.7). vlcd1 conne ct to vdd
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 75 preliminary version 1.2 8 8 8 timers 8.1 watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter des igned for monitoring program execution. if the prog ram goes into the unknown status by noise interference, wdt overf low signal raises and resets mcu. the instruction t hat clears the watchdog timer (? b0bset fwdrst ?) should be execu ted within a certain period. if an instruction that clears the watchdog timer is not executed within the period an d the watchdog timer overflows, reset signal is gen erated and system is restarted. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx 0 read/write r/w r/w r/w r/w r/w r/w r/w - after reset 0 0 0 0 0 0 0 - bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapte r.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. watchdog timer overflow table. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v note: the watchdog timer can be enabled or disabled by the code option.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 76 preliminary version 1.2 watchdog timer application note is as following. before clearing watchdog timer, check i/o status a nd check ram contents can improve system error. don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main r outine fail. clearing watchdog timer program is only at one par t of the program. this way is the best structure to enhance the watchdog timer function. example: an operation of watchdog timer is as follo wing. to clear the watchdog timer counter in the to p of the main routine of the program. main: ? ; check i/o. ? ; check ram err: jmp $ ; i/o or ram error. program jump here a nd don?t ; clear watchdog. wait watchdog timer overflow t o reset ic. correct: ; i/o and ram are correct. clear watchdo g timer and ; execute program. b0bset fwdrst ; only one clearing watchdog timer o f whole program. ? call sub1 call sub2 ? ? ? jmp main
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 77 preliminary version 1.2 8.2 timer 0 (t0) 8.2.1 overview the t0 is an 8-bit binary up timer and event counte r. if t0 timer occurs an overflow (from ffh to 00h) , it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purposes of the t0 timer is as following. 8-bit programmable up counting timer: generates interrupts at specific time intervals bas ed on the selected clock frequency. rtc timer: generates interrupts at real time intervals based o n the selected clock source. rtc function is only available in t0tb=1. green mode wakeup function: t0 can be green mode wake-up time as t0enb = 1. sy stem will be wake-up by t0 time out. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus t0enb rtc t0tb note: in rtc mode, the t0 interval time is fixed at 0.5 sec and isn?t controlled by t0c.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 78 preliminary version 1.2 8.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0t b read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc, t0 will be 0.5 sec rtc (low clock m ust be 32768 cyrstal). bit 1 tc0gn: enable tc0 green mode wake up function 0 = disable. 1 = enable. bit 2 tc0x8: tc0 internal clock source control bit. 0 = tc0 internal clock source is fcpu. tc0rate is f rom fcpu/2~fcpu/256. 1 = tc0 internal clock source is fosc. tc0rate is f rom fosc/1~fosc/128. bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is f rom fcpu/2~fcpu/256. 1 = tc1 internal clock source is fosc. tc1rate is f rom fosc/1~fosc/128. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. note: t0rate is not available in rtc mode. the t0 i nterval time is fixed at 0.5 sec.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 79 preliminary version 1.2 8.2.3 t0c counting register t0c is an 8-bit counter register for t0 interval ti me control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) example: to set 10ms interval time for t0 interrupt . high clock is external 4mhz. fcpu=fosc/4. select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval ti me * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of t0. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) t0rate t0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us note: t0c is not available in rtc mode. the t0 inte rval time is fixed at 0.5 sec.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 80 preliminary version 1.2 8.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. stop t0 timer counting, disable t0 interrupt functi on and clear t0 interrupt request flag. b0bclr ft0enb ; t0 timer. b0bclr ft0ien ; t0 interrupt function is disabled. b0bclr ft0irq ; t0 interrupt request flag is clear ed. set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bits exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. b0mov t0m,a ; t0 timer is disabled. set t0 clock source from fcpu or rtc. b0bclr ft0tb ; select t0 fcpu clock source. or b0bset ft0tb ; select t0 rtc clock source. set t0 interrupt interval time. mov a,#7fh b0mov t0c,a ; set t0c value. set t0 timer function mode. b0bset ft0ien ; enable t0 interrupt function. enable t0 timer. b0bset ft0enb ; enable t0 timer.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 81 preliminary version 1.2 8.3 timer/counter 0 (tc0) 8.3.1 overview the tc0 is an 8-bit binary up counting timer. tc0 c lock sources came internal clock for counting a pre cision time. the internal clock source is from fcpu or fosc controll ed by tc0x8 flag to get faster clock source (fosc). if tc0 timer occurs an overflow, it will continue counting and i ssue a time-out signal to trigger tc0 interrupt to request interrupt service. tc0 overflow time is 0xff to 0x00 normally . under pwm mode, tc0 overflow is decided by pwm cy cle controlled by aload0 and tc0out bits. the main purposes of the tc0 timer is as following. 8-bit programmable up counting timer: generates interrupts at specific time intervals bas ed on the selected clock frequency. green mode wake-up function: tc0 can be green mode wake-up timer. system will be wake-up by tc0 time out. buzzer output pwm output
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 82 preliminary version 1.2 8.3.2 tc0m mode register 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 - aload0 tc0out pwm0out read/write r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 0 pwm0out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc0ou t, aload0 bits. bit 1 tc0out: tc0 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.4 is i/o function. 1 = enable, p5.4 is output tc0out signal. bit 2 aload0: auto-reload control bit. only valid when pwm0out = 0. 0 = disable tc0 auto-reload function. 1 = enable tc0 auto-reload function. bit [6:4] tc0rate[2:0]: tc0 internal clock select bits. tc0rate [2:0] tc0x8 = 0 tc0x8 = 1 000 fcpu / 256 fosc / 128 001 fcpu / 128 fosc / 64 010 fcpu / 64 fosc / 32 011 fcpu / 32 fosc / 16 100 fcpu / 16 fosc / 8 101 fcpu / 8 fosc / 4 110 fcpu / 4 fosc / 2 111 fcpu / 2 fosc / 1 bit 7 tc0enb: tc0 counter control bit. 0 = disable tc0 timer. 1 = enable tc0 timer.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 83 preliminary version 1.2 8.3.3 tc1x8, tc0x8, tc0gn flags 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0t b read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc. bit 1 tc0gn: enable tc0 green mode wake up function 0 = disable. 1 = enable. bit 2 tc0x8: tc0 internal clock source control bit. 0 = tc0 internal clock source is fcpu. tc0rate is f rom fcpu/2~fcpu/256. 1 = tc0 internal clock source is fosc. tc0rate is f rom fosc/1~fosc/128. bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is f rom fcpu/2~fcpu/256. 1 = tc1 internal clock source is fosc. tc1rate is f rom fosc/1~fosc/128. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 84 preliminary version 1.2 8.3.4 tc0c counting register tc0c is an 8-bit counter register for tc0 interval time control. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc0c initial value is as following. tc0c initial value = 256 - (tc0 interrupt interva l time * input clock) tc0x8 tc0c valid value tc0c value binary type remark 0 (fcpu/2~ fcpu/256) 0x00~0xff 00000000b~11111111b overflow per 256 count 1 (fosc/1~ fosc/128) 0x00~0xff 00000000b~11111111b overflow per 256 count
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 85 preliminary version 1.2 example: to set 10ms interval time for tc0 interrup t. tc0 clock source is fcpu (tc0ks=0, tc0x8=0) and no pwm output (pwm0=0). high clock is external 4mhz . fcpu=fosc/4. select tc0rate=010 (fcpu/64). tc0c initial value = n - (tc0 interrupt interval ti me * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of tc0, tc0x8 = 0. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us the basic timer table interval time of tc0, tc0x8 = 1. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fosc/128 8.192 ms 32 us 1000 ms 7812.5 us 001 fosc/64 4.096 ms 16 us 500 ms 3906.25 us 010 fosc/32 2.048 ms 8 us 250 ms 1953.125 us 011 fosc/16 1.024 ms 4 us 125 ms 976.563 us 100 fosc/8 0.512 ms 2 us 62.5 ms 488.281 us 101 fosc/4 0.256 ms 1 us 31.25 ms 244.141 us 110 fosc/2 0.128 ms 0.5 us 15.625 ms 122.07 us 111 fosc/1 0.064 ms 0.25 us 7.813 ms 61.035 us
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 86 preliminary version 1.2 8.3.5 tc0r auto-load register tc0 timer is with auto-load function controlled by aload0 bit of tc0m. when tc0c overflow occurring, t c0r value will load to tc0c by system. it is easy to generate an accurate time, and users don?t reset tc0c durin g interrupt service routine. note: under pwm mode, auto-load is enabled automati cally. the aload0 bit is selecting overflow boundary. 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc0r initial value is as following. tc0r initial value = 256 - (tc0 interrupt interva l time * input clock) these parameters decide tc0 overflow time and valid value as follow table. tc0x8 tc0r valid value tc0r value binary type 0 (fcpu/2~fcpu/256) 0x00~0xff 00000000b~11111111b 1 (fosc/1~fosc/128) 0x00~0xff 00000000b~11111111b example: to set 10ms interval time for tc0 interrup t. tc0 clock source is fcpu (tc0x8=0) and no pwm output (pwm0=0). high clock is external 4mhz. fcpu= fosc/4. select tc0rate=010 (fcpu/64). tc0r initial value = 256 - (tc0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 87 preliminary version 1.2 8.3.6 tc0 clock frequency output (buzzer) buzzer output (tc0out) is from tc0 timer/counter fr equency output function. by setting the tc0 clock f requency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-disable. the tc0out f requency is divided by 2 from tc0 interval time. tc0out frequen cy is 1/2 tc0 frequency. the tc0 clock has many com binations and easily to make difference frequency. the tc0out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc0 overflow clock tc0out (buzzer) output clock example: setup tc0out output from tc0 to tc0out (p5 .4). the external high-speed clock is 4mhz. the tc0out frequency is 0.5khz. because the tc0out sign al is divided by 2, set the tc0 clock to 1khz. the tc0 clock source is from external oscillator clock. t0c rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 131. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and dis able p5.4 i/o function b0bset faload1 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer note: buzzer output is enable, and ?pwm0out? must b e ?0?.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 88 preliminary version 1.2 8.3.7 tc0 timer operation sequence tc0 timer operation includes timer interrupt, event counter, tc0out and pwm. the sequence of setup tc0 timer is as following. stop tc0 timer counting, disable tc0 interrupt func tion and clear tc0 interrupt request flag. b0bclr ftc0enb ; tc0 timer, tc0out and pwm stop. b0bclr ftc0ien ; tc0 interrupt function is disable d. b0bclr ftc0irq ; tc0 interrupt request flag is cle ared. set tc0 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc0 rate control bits exist in bit4~bit6 of tc0m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc0m,a ; tc0 interrupt function is disabled. set tc0 timer clock urce. b0bclr ftc0x8 ; select tc0 fcpu internal clock sou rce. or b0bset ftc0x8 ; select tc0 fosc internal clock sou rce. note: tc0x8 is useless in tc0 external clock source mode. set tc0 timer auto-load mode. b0bclr faload0 ; enable tc0 auto reload function. or b0bset faload0 ; disable tc0 auto reload function. set tc0 interrupt interval time, tc0out (buzzer) fr equency or pwm duty cycle. ; set tc0 interrupt interval time, tc0out (buzzer) frequency or pwm duty. mov a,#7fh ; tc0c and tc0r value is decided by tc0 mode. b0mov tc0c,a ; set tc0c value. b0mov tc0r,a ; set tc0r value under auto reload mod e or pwm mode.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 89 preliminary version 1.2 set tc0 timer function mode. b0bset ftc0ien ; enable tc0 interrupt function. or b0bset ftc0out ; enable tc0out (buzzer) function. or b0bset fpwm0out ; enable pwm function. or b0bset ftc0gn ; enable tc0 green mode wake-up funct ion. enable tc0 timer. b0bset ftc0enb ; enable tc0 timer.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 90 preliminary version 1.2 8.4 timer/counter 1 (tc1) 8.4.1 overview the tc1 is an 8-bit binary up counting timer. tc1 c lock source came from internal clock for counting a precision time. the internal clock source is from fcpu or fosc cont rolled by tc1x8 flag to get faster clock source (fo sc). if tc1 timer occurs an overflow, it will continue counting and i ssue a time-out signal to trigger tc1 interrupt to request interrupt service. tc1 overflow time is 0xff to 0x00 normally . under pwm mode, tc1 overflow is decided by pwm cy cle controlled by aload1 and tc1out bits. the main purposes of the tc1 timer is as following. 8-bit programmable up counting timer: generates interrupts at specific time intervals bas ed on the selected clock frequency. buzzer output pwm output fcpu tc1 rate (fcpu/2~fcpu/256) fosc tc1 rate (fosc/1~fosc/128) tc1x8 tc1enb cpum0,1 tc1c 8-bit binary up counting counter tc1r reload data buffer compare aload1 rs tc1 time out auto. reload tc1 / 2 buzzer internal p5.3 i/o circuit p5.3 pwm pwm1out tc1out aload1, tc1out load
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 91 preliminary version 1.2 8.4.2 tc1m mode register 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1rate1 tc1rate0 - aload1 tc1out pwm1out read/write r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 0 pwm1out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc1ou t, aload1 bits. bit 1 tc1out: tc1 time out toggle signal output control bit. only valid when pwm1out = 0. 0 = disable, p5.3 is i/o function. 1 = enable, p5.3 is output tc1out signal. bit 2 aload1: auto-reload control bit. only valid when pwm1out = 0. 0 = disable tc1 auto-reload function. 1 = enable tc1 auto-reload function. bit [6:4] tc1rate[2:0]: tc1 internal clock select bits. tc1rate [2:0] tc1x8 = 0 tc1x8 = 1 000 fcpu / 256 fosc / 128 001 fcpu / 128 fosc / 64 010 fcpu / 64 fosc / 32 011 fcpu / 32 fosc / 16 100 fcpu / 16 fosc / 8 101 fcpu / 8 fosc / 4 110 fcpu / 4 fosc / 2 111 fcpu / 2 fosc / 1 bit 7 tc1enb: tc1 counter control bit. 0 = disable tc1 timer. 1 = enable tc1 timer. 8.4.3 tc1x8 flag 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m - - - - tc1x8 - - - read/write - - - - r/w - - - after reset - - - - 0 - - - bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is f rom fcpu/2~fcpu/256. 1 = tc1 internal clock source is fosc. tc1rate is f rom fosc/1~fosc/128.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 92 preliminary version 1.2 8.4.4 tc1c counting register tc1c is an 8-bit counter register for tc1 interval time control. 0ddh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc1c initial value is as following. tc1c initial value = 256 - (tc1 interrupt interva l time * input clock) these parameters decide tc1 overflow time and valid value as follow table. tc1x8 tc1c valid value tc1c value binary type remark 0 (fcpu/2~fcpu/256) 0x00~0xff 00000000b~11111111b overflow per 256 count 1 (fosc/1~fosc/128) 0x00~0xff 00000000b~11111111b overflow per 256 count example: to set 10ms interval time for tc1 interrup t. tc1 clock source is fcpu and no pwm output (pwm1=0). high clock is external 4mhz. fcpu=fosc/4. select tc1rate=010 (fcpu/64). tc1c initial value = 256 - (tc1 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 93 preliminary version 1.2 the basic timer table interval time of tc1, tc1x8 = 0. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us the basic timer table interval time of tc1, tc1x8 = 1. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fosc/128 8.192 ms 32 us 1000 ms 7812.5 us 001 fosc/64 4.096 ms 16 us 500 ms 3906.25 us 010 fosc/32 2.048 ms 8 us 250 ms 1953.125 us 011 fosc/16 1.024 ms 4 us 125 ms 976.563 us 100 fosc/8 0.512 ms 2 us 62.5 ms 488.281 us 101 fosc/4 0.256 ms 1 us 31.25 ms 244.141 us 110 fosc/2 0.128 ms 0.5 us 15.625 ms 122.07 us 111 fosc/1 0.064 ms 0.25 us 7.813 ms 61.035 us
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 94 preliminary version 1.2 8.4.5 tc1r auto-load register tc1 timer is with auto-load function controlled by aload1 bit of tc1m. when tc1c overflow occurring, t c1r value will load to tc1c by system. it is easy to generate an accurate time, and users don?t reset tc1c durin g interrupt service routine. note: under pwm mode, auto-load is enabled automati cally. the aload1 bit is selecting overflow boundary. 0deh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc1r initial value is as following. tc1r initial value = 256 - (tc1 interrupt interva l time * input clock) these parameters decide tc1 overflow time and valid value as follow table. tc1x8 tc1r valid value tc1r value binary type 0 (fcpu/2~fcpu/256) 0x00~0xff 00000000b~11111111b 1 (fosc/1~fosc/128) 0x00~0xff 00000000b~11111111b example: to set 10ms interval time for tc1 interrup t. tc1 clock source is fcpu (tc1x8=0) and no pwm output (pwm1=0). high clock is external 4mhz. fcpu= fosc/4. select tc1rate=010 (fcpu/64). tc1r initial value = 256 - (tc1 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 95 preliminary version 1.2 8.4.6 tc1 clock frequency output (buzzer) buzzer output (tc1out) is from tc1 timer/counter fr equency output function. by setting the tc1 clock f requency, the clock signal is output to p5.3 and the p5.3 general purpose i/o function is auto-disable. the tc1out f requency is divided by 2 from tc1 interval time. tc1out frequen cy is 1/2 tc1 frequency. the tc1 clock has many com binations and easily to make difference frequency. the tc1out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc1 overflow clock tc1out (buzzer) output clock example: setup tc1out output from tc1 to tc1out (p5 .3). the external high-speed clock is 4mhz. the tc1out frequency is 0.5khz. because the tc1out sign al is divided by 2, set the tc1 clock to 1khz. the tc1 clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 131. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.3 and dis able p5.3 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer note: buzzer output is enable, and ?pwm1out? must b e ?0?.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 96 preliminary version 1.2 8.4.7 tc1 timer operation sequence tc1 timer operation includes timer interrupt, event counter, tc1out and pwm. the sequence of setup tc1 timer is as following. stop tc1 timer counting, disable tc1 interrupt func tion and clear tc1 interrupt request flag. b0bclr ftc1enb ; tc1 timer, tc1out and pwm stop. b0bclr ftc1ien ; tc1 interrupt function is disable d. b0bclr ftc1irq ; tc1 interrupt request flag is cle ared. set tc1 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc1 rate control bits exist in bit4~bit6 of tc1m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc1m,a ; tc1 timer is disabled. set tc1 timer clock source. ; select tc1 fcpu / fosc internal clock source . b0bclr ftc1x8 ; select tc1 fcpu internal clock sou rce. or b0bset ftc1x8 ; select tc1 fosc internal clock sou rce. note: tc1x8 is useless in tc1 external clock source mode. set tc1 timer auto-load mode. b0bclr faload1 ; enable tc1 auto reload function. or b0bset faload1 ; disable tc1 auto reload function. set tc1 interrupt interval time, tc1out (buzzer) fr equency or pwm duty cycle. ; set tc1 interrupt interval time, tc1out (buzzer) frequency or pwm duty. mov a,#7fh ; tc1c and tc1r value is decided by tc1 mode. b0mov tc1c,a ; set tc1c value. b0mov tc1r,a ; set tc1r value under auto reload mod e or pwm mode.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 97 preliminary version 1.2 set tc1 timer function mode. b0bset ftc1ien ; enable tc1 interrupt function. or b0bset ftc1out ; enable tc1out (buzzer) function. or b0bset fpwm1out ; enable pwm function. enable tc1 timer. b0bset ftc1enb ; enable tc1 timer.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 98 preliminary version 1.2 8.5 pwm0 mode 8.5.1 overview pwm function is generated by tc0 timer counter and output the pwm signal to pwm0out pin (p5.4). the 8- bit counter counts modulus 256 bits. the value of the 8 -bit counter (tc0c) is compared to the contents of the reference register (tc0r). when the reference register value (tc0r) is equal to the counter value (tc0c), the pw m output goes low. when the counter reaches zero, the pwm output is forced high. the ratio (duty) of the pwm0 output is tc0r/256. pwm duty range tc0c valid value tc0r valid bits value max. pwm frequency (fcpu = 4mhz) remark 0/256~255/256 0x00~0xff 0x00~0xff 7.8125k overflow per 256 count the output duty of pwm is with different tc0r. duty range is from 0/256~255/256. tc0 clock tc0r=00h tc0r=01h tc0r=80h tc0r=ffh 0 1 128 254 255 0 1 128 254 255 low low low high high low high
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 99 preliminary version 1.2 8.5.2 tc0irq and pwm duty in pwm mode, the frequency of tc0irq is depended on pwm duty range. from following diagram, the tc0irq frequency is related with pwm duty. 8.5.3 pwm program example example: setup pwm0 output from tc0 to pwm0out (p5. 4). the external high-speed oscillator clock is 4mhz. fcpu = fosc/4. the duty of pwm is 30/256. the pwm frequency is about 1khz. the pwm clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 30. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc0c,a b0mov tc0r,a b0bset fpwm0out ; enable pwm0 output to p5.4 and d isable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer note: the tc0r is write-only register. don?t proces s them using incms, decms instructions. example: modify tc0r registers? value. mov a, #30h ; input a number using b0mov instructi on. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc0r, a note: the pwm can work with interrupt request. tc0 overflow, tc0irq = 1 0xff tc0c value 0x00 pwm0 output (duty range 0~255)
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 100 preliminary version 1.2 8.5.4 pwm0 duty changing notice in pwm mode, the system will compare tc0c and tc0r all the time. when tc0c SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 101 preliminary version 1.2 8.6 pwm1 mode 8.6.1 overview pwm function is generated by tc1 timer counter and output the pwm signal to pwm1out pin (p5.3). the 8- bit counter counts modulus 256 bits. the value of the 8 -bit counter (tc1c) is compared to the contents of the reference register (tc1r). when the reference register value (tc1r) is equal to the counter value (tc1c), the pw m output goes low. when the counter reaches zero, the pwm output is forced high. the ratio (duty) of the pwm1 output is tc1r/256, pwm duty range tc1c valid value tc1r valid bits value max. pwm frequency (fcpu = 4mhz) remark 0/256~255/256 0x00~0xff 0x00~0xff 7.8125k overflow per 256 count the output duty of pwm is with different tc1r. duty range is from 0/256~255/256. tc1 clock tc1r=00h tc1r=01h tc1r=80h tc1r=ffh 0 1 128 254 255 0 1 128 254 255 low low low high high low high
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 102 preliminary version 1.2 8.6.2 tc1irq and pwm duty in pwm mode, the frequency of tc1irq is depended on pwm duty range. from following diagram, the tc1irq frequency is related with pwm duty. 8.6.3 pwm program example example: setup pwm1 output from tc1 to pwm1out (p5. 3). the external high-speed oscillator clock is 4mhz. fcpu = fosc/4. the duty of pwm is 30/256. the pwm frequency is about 1khz. the pwm clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 30. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc1c,a b0mov tc1r,a b0bset fpwm1out ; enable pwm1 output to p5.3 and d isable p5.3 i/o function b0bset ftc1enb ; enable tc1 timer note: the tc1r is write-only register. don?t proces s them using incms, decms instructions. example: modify tc1r registers? value. mov a, #30h ; input a number using b0mov instructi on. b0mov tc1r, a incms buf0 ; get the new tc1r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc1r, a note: the pwm can work with interrupt request. tc1 overflow, tc1irq = 1 0xff tc1c value 0x00 pwm1 output (duty range 0~255)
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 103 preliminary version 1.2 8.6.4 pwm1 duty changing notice in pwm mode, the system will compare tc1c and tc1r all the time. when tc1c SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 104 preliminary version 1.2 8.7 bzo timer SN8P1989 build in a buzzer output with controllable frequency change by bzc and bzm register and outpu t in bzo pin. 09ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bzm bzoenb bzorate2 bzorate1 bzorate1 - bzox8 read/write r/w r/w r/w r/w - r/w after reset 0 0 0 0 - 0 bit 2 bzox8: bzo internal clock source control bit. 0 = bzo internal clock source is fcpu. bzorate is f rom fcpu/2~fcpu/256. 1 = bzo internal clock source is fosc. bzorate is f rom fosc/1~fosc/128. bit [6:4] bzorate[2:0]: bzo internal clock select bits. bzorate [2:0] bzox8 = 0 bzox8 = 1 000 fcpu / 256 fosc / 128 001 fcpu / 128 fosc / 64 010 fcpu / 64 fosc / 32 011 fcpu / 32 fosc / 16 100 fcpu / 16 fosc / 8 101 fcpu / 8 fosc / 4 110 fcpu / 4 fosc / 2 111 fcpu / 2 fosc / 1 bit 7 bzoenb: bzo buzzer-output enable control bit. 0 = disable bzo buzzer output. 1 = enable bzo buzzer output 09bh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bzc bzc7 bzc6 bzc5 bzc4 bzc3 bzc2 bzc1 bzc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bzc initial value = n - (bzo interval time * inpu t clock) example: to set 6.25k (160us) buzzer output in bzo. the bzo counter clock source is fcpu/2 (bzox8=0, bzorate[2:0]=111). high clock is external 4mhz. fc pu=fosc/4. bzc initial value = 256 - (buzzer interrupt interv al time * input clock) = 256 - (160us * 4mhz / 4 / 2/2) = 256 - (160*10 -6 * 4 * 10 6 / 4 / 2/2) = 256-40 = 216 = d8h the basic timer table of bzo output clcok. bzc bzox8 bz0rate bz clock bzo output frequency d8h 0 111 fcpu/2 6.25k fbh 0 111 fcpu/2 50k fbh 1 101 fosc/4 100k ffh 0 111 fcpu/2 250k
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 105 preliminary version 1.2 9 9 9 lcd driver 9.1 overview there are 4 common pins and 28 segment pins in the SN8P1989. the lcd scan timing is 1/4 duty and 1/3 b ias structure to yield 112 dots lcd driver. user can ad d resistance between vlcd/v2/v1 for more driving cu rrent. basic lcd circuit mcu vlcd v2 v1 vss 100kohm 100kohm 100kohm vss 0.1uf 0.1uf 0.1uf lxin lxout vss 32768hz 10pf 10pf com0~com3 seg0~seg27 lcd panel vdd optional
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 106 preliminary version 1.2 9.2 lcdm1 register lcdm1 register initial value = xx0x 0xxx 089h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcdm1 - - lcdbnk - lcdenb - p2hseg p2lseg r/w - - r/w - r/w - r/w r/w after reset - - 0 - 0 - 0 0 bit5 lcdbnk: lcd blank control bit. 0 = normal display 1 = all of the lcd dots off. bit3 lcdenb: lcd driver enable control bit. 0 = disable lcd function 1 = enable lcd function bit1 p2hseg : seg20~23 lcd/io selection bit. 0 = seg20~23 as lcd function. vlcd1 connect to vlcd 1 = seg20~23 as io function (p2.0~p2.3). vlcd1 conne ct to vdd bit0 p2lseg : seg24~27 lcd/io selection bit. 0 = seg24~27 as lcd function. vlcd1 connect to vlcd 1 = seg24~27 as io function (p2.4~p2.7). vlcd2 conne ct to vdd
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 107 preliminary version 1.2 9.3 lcd timing f-frame = external low clock / 512 ex. external low clock is 32768hz. the f-frame is 3 2768hz/512 = 64hz . note: the clock source of lcd driver is external lo w clock. lcd drive waveform, 1/4 duty, 1/3 bias vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd com0 com1 com2 com3 seg0 (1010b) seg0 (0101b) 1 frame 1 frame lcd clock off on off off off off off off off on on on on on on on
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 108 preliminary version 1.2 9.4 lcd ram location ram bank 15?s address vs. common/segment pin location bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 com0 com1 com2 com3 - - - - seg 0 00h.0 00h.1 00h.2 00h.3 - - - - seg 1 01h.0 01h.1 01h.2 01h.3 - - - - seg 2 02h.0 02h.1 02h.2 02h.3 - - - - seg 3 03h.0 03h.1 03h.2 03h.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - seg 1c 1ch.0 1ch.1 1ch.2 1ch.3 - - - - example: enable lcd function. set the lcd control bit (lcdenb) and program lcd r am to display lcd panel. b0bset flcdenb ; lcd driver. 9.5 option register description option initial value = xxxx xxx0 088h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 option - - - - - - - rclk r/w - - - - - - - r/w after reset - - - - - - - 0 rclk: external low oscillator type control bit. 0 = crystal mode 1 = rc mode. note1: circuit diagram when rclk=0 ?external low c lock sets as crystal mode.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 109 preliminary version 1.2 note2: circuit diagram when ?rclk=1? will enable ex ternal low clock sets as rc mode. connect the c as near as possible to the vss pin o f micro-controller. the frequency of external low r c is decided by the capacitor value. adjust capacitor value to about 32khz frequency.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 110 preliminary version 1.2 1 1 1 0 0 0 regulator, pgia and adc 10.1 overview the SN8P1989 has a built-in voltage regulator (reg) to support a stable voltage 3.8v from pin avddr and 3.0v from pin ave+ with maximum 10ma current driving capacit y. this reg provides stable voltage for internal ci rcuits (pgia, adc) and external sensor (load cell or thermi stor). the SN8P1989 series also integrated ? analog-to-digital converters (adc) to achieve 16-bit performance and u p to 62500-step resolution. the adc has 1 different input channel modes: one fully differential inputs . this adc is optimized for measuring low-level unipolar or bipola r signals in weight scale and medical applications. a very low noise chopper-stabilized programmable gain instrumen tation amplifier (pgia) with selectable gains of 1x, 12.5x, 50x, 100x, and 200x in the adc to accommodate these applications. 10.2 analog input following diagram illustrates a block diagram of the pgia and adc module. the front end consists of a m ultiplexer for input channel selection, a pgia (programmable gain i nstrumentation amplifier), and the ? adc modulator. to obtain maximum range of adc output, the adc maxim um input signal voltage v (x+, x-) should be close t o but can?t over the reference voltage v(r+, r-), choosin g a suitable reference voltage and a suitable gain of pgia can reach this purpose. the relative control bits are r vs [1:0] bits (reference voltage selection) in adc1 6m register and gs[2:0] bits (gain selection) in ampm register. ai1+ ai1- ampchs[3:0] pgia 1x~200x adc16m[7:0] x- x+ 16-bit adc ao+ ao- r+/r- 0.64v adc ref. voltage ampm[7:0] r ao+ r ao- c x 0.80v 0.40v 0.32v
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 111 preliminary version 1.2 10.3 voltage regulator (reg) SN8P1989 was built in a reg, which can provide a st able 3.8v (pin avddr) and 3.0v/1.5v (pin ave+) with maximum 10ma current driving capacity. register regm can en able or disable reg and controls reg working mode. because the power of pgia and adc is come from avddr, turn on avddr (avddrenb = 1) first before enabling pgia and adc. the avddr voltage was regulated from vdd. in a ddition, it will need at least 30ms delay for outpu t voltage stabilization after set regenb to high. 10.3.1 regm- regulator mode register 095h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 regm acmenb avddrenb avenb avesel1 avesel0 - - regenb r/w r/w r/w r/w r/w r/w - - r/w after reset 0 0 0 0 0 - - 0 bit0: regenb: regulator function enable control bit. 0 = disable internal regulator 1 = enable internal regular. bit3,4 avesel[1:0]: ave+ voltage selection control bit. avesel1 avesel0 ave+ voltage 1 1 3.0v 1 0 2.4v 0 1 1.5v 0 0 reserved bit5: avenb: ave+ voltage output control bit. 0 = disable ave+ output voltage 1 = enable ave+ output voltage bit6: avddrenb: regulator (avddr) voltage enable control bit. 0 = disable avddr output voltage 3.8v 1 = enable avddr output voltage 3.8v bit7: acmenb: analog common mode (acm) voltage enable control bi t. 0 = disable analog common mode and acm output volta ge 1.2v 1 = enable analog common mode and acm output voltag e 1.2v note1: 30ms delay is necessary for output voltage s tabilization after set regenb = ?1?. note2: before enable regulator , must enable band g ap reference (bgrenb=1) first. note3: before enable pgia and adc , must enable ban d gap reference (bgrenb=1), acm (acmenb=1) and avddr(avddrenb). note4: regulator, pgia and adc can work in slow mod e, but ampcks register value must be reassigned .
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 112 preliminary version 1.2 10.4 pgia -programmable gain instrumentation amplif ier SN8P1989 includes a low noise chopper-stabilized pr ogrammable gain instrumentation amplifier (pgia) wi th selection gains of 1x, 12.5x, 50x, 100x, and 200x by register ampm. the pgia also provides two types channel sel ection mode: (1) one fully differential input (2) two single-end ed inputs, it was defined by register ampchs. 10.4.1 ampm- amplifier mode register 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampm - bgrenb fds1 fds0 gs2 gs1 gs0 ampenb r/w - r/w r/w r/w r/w r/w r/w r/w after reset - 0 1 1 1 1 1 0 bit0: ampenb: pgia function enable control bit. 0 = disable pgia function 1 = enable pgia function bit[3:1]: gs [2:0]: pgia gain selection control bit gs [2:0] pgia gain 000 12.5 001 50 010 100 011 200 100,101,110 reserved 111 1 note: when selected gain is 1x, pgia can be disable d (ampenb=0) for power saving. bit[5:4] fds [1:0]: chopper low frequency setting note:set fds[1:0] = ?11? for all applications. bit6: bgrenb: band gap reference voltage enable control bit. 0 = disable band gap reference voltage 1 = enable band gap reference voltage note1: band gap reference voltage must be enable (f brgenb), before following function accessing 1. regulator. 2. pgia function. 3. 16- bit adc function. 4. low battery detect function note2: pgia can?t work in slow mode, unless gain se lection is 1x.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 113 preliminary version 1.2 10.4.2 ampcks- pgia clock selection 092h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampcks - - - - - ampcks2 ampcks1 ampcks0 r/w - - - - - w w w after reset - - - - - 0 0 0 bit[2:0] ampcks [2:0] register sets the pgia chopper working clock. the s uggestion chopper clock is 1.95k hz.@ 4mhz, 1.74k @ 3.58mhz. pgia clock= fcpu / 32 / (2^ampcks) refer to the following table for ampcks [2:0] regis ter value setting in different fosc frequency. high clock ampcks2 amcks1 ampcks0 2m 3.58m 4m 8m 0 0 0 15.625k 27.968k 31.25k 62.5k 0 0 1 7.8125k 13.98k 15.625k 31.25k 0 1 0 3.90625k 6.99k 7.8125k 15.625k 0 1 1 1.953125k 3.49k 3.90625k 7.8125k 1 0 0 976hz 1.748k 1.953125k 3.90625k 1 0 1 488hz 874hz 976hz 1.953125k 1 1 0 244hz 437hz 488hz 976hz 1 1 1 122hz 218hz 244hz 488hz note: in general application, set pgia chopper work ing clock is ~2k hz, but set clock to 250hz when hi gh clock is 32768 crystal or in external low clock mod e.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 114 preliminary version 1.2 10.4.3 ampchs-pgia channel selection 091h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampchs - - - - adc16chs3 adc16chs2 adc16chs1 adc16chs0 r/w - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 adc16chs0: pgia channel selection adc16chs [3:0] selected channel v (x+, x-) output input-signal type 0000 ai1+, ai1- v (ai1+, ai1-) pgia gain differential 0110 acm, acm v (acm, acm) pgia gain input-short others reserved - - note 1: v (ai+, ai-) = (ai+ voltage - ai- voltage) note 2: the purpose of input-short mode is only for pgia offset testing. note 3: when reg is disable or system in stop mode, signal on analog input pins must be zero (?0?v, including ai+, ai-, x+, x-, r+ and r-) or it will c ause the current consumption from these pins.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 115 preliminary version 1.2 10.5 16-bit adc 10.5.1 adc16m- adc mode register 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc16m - - - - irvs rvs1 rvs0 adc16enb - - - - r/w r/w r/w r/w - 0 0 0 0 bit0: adc16enb: adc function control bit: 0 = disable 16-bit adc, 1 = enable 16-bit adc bit[2:1]: rvs [1:0] : adc reference voltage selection bit 1 00 = selection adc reference voltage from external reference r+,r-. 10 = selection adc reference voltage from internal reference bit3: irvs: internal reference voltage selection. 0 = internal reference voltage v(ref+,ref-) is ave+ /0.133 (when ave+=3.0v, v(ref+,ref-)=0.4v) 1 = internal reference voltage v(ref+,ref-) is ave+ /0.266 (when ave+=3.0v, v(ref+,ref-)=0.8v) bit4: always set to ?0? ad reference voltage ad channel input irvs rvs1 rvs0 avesel[1:0] ref+ ref- adcin+ adcin- note x 0 0 - r+ r- external ref. voltage 0 1 0 11 (ave+=3.0v) 0.8v 0.4v v (x+, x-) < 0.4v 0 1 0 10 (ave+=2.4v) 0.64v 0.32v v (x+, x-) < 0.32v 1 1 0 11 (ave+=3.0v) 1.2v 0.4v v (x+, x-) < 0.8v 1 1 0 10 (ave+=2.4v) 0.96v 0.32v v (x+, x-) < 0.64v 1 1 0 01 (ave+=1.5v) 0.6v 0.2v x+ x- v (x+, x-) < 0.4v note1: the adc conversion data is combined with adc dh and adcdl register in 2?s compliment with sign bit numerical format, and bit adcb15 is the si gn bit of adc data. refer to following formula to calculate adc conversion data value. note2: the internal reference voltage is divided fr om ave+, so the voltage will follow the changing wi th ave+(3.0v/2.4v/1.5v) which selected by avesel[1:0]. note1: the ad c conversion data is combined with adcdh and adcdl register in 2?s compliment with sign bit numerical format, and bit adcb15 is the si gn bit of adc data. refer to following formula to calculate adc conversion data value.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 116 preliminary version 1.2 31250 ) ( ) ( ) ( ) ( ) ( ) ( 31250 ) ( ) ( ) ( ) ( ) ( ) ( x ref ref adcin adcin iondata adcconvers adcin adcin x ref ref adcin adcin iondata adcconvers adcin adcin ? ? + ? ? + ? = ? ? < + ? ? + ? ? + + = ? ? > + 10.5.2 adcks- adc clock register 094h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcks adcks7 adcks6 adcks5 adcks4 adcks3 adcks2 adcks1 ad cks0 w w w w w w w w after reset 0 0 0 0 0 0 0 0 adcks [7:0] register sets the adc working clock, the suggestion adc clock is 100k hz. refer the following table for adcks [7:0] register value setting in different fosc frequency. adc clock= (fosc / (256-adcks [7:0]))/2 adcks [7:0] f osc adc working clock 246 4m (4m / 10)/2 = 200k 236 4m (4m / 20)/2 = 100k 243 4m (4m / 13)/2 = 154k 231 4m (4m / 25)/2 = 80k adcks [7:0] f osc adc working clock 236 8m (8m / 20)/2 = 200k 216 8m (8m / 40)/2 = 100k 231 8m (8m / 25)/2 = 160k 206 8m (8m / 50)/2 = 80k note: in general application, adc working clock is 100k hz.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 117 preliminary version 1.2 10.5.3 adcdl- adc low-byte data register 098h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdl adcb7 adcb6 adcb5 adcb4 adcb3 adcb2 adcb1 adcb0 r r r r r r r r after reset 0 0 0 0 0 0 0 0 10.5.4 adcdh- adc high-byte data register 099h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdh adcb15 adcb14 adcb13 adcb12 adcb11 adcb10 adcb8 adc b9 r r r r r r r r after reset 0 0 0 0 0 0 0 0 adcdl [7:0]: output low byte data of adc conversion word. adcdh [7:0]: output high byte data of adc conversion word. . note1: adcdl [7:0] and adcdh [7:0] are both read on ly registers. note2: the adc conversion data is combined with adc dh, adcdl in 2?s compliment with sign bit numerical format, and bit adcb15 is the sign bit of adc data. adcb15=0 means data is positive value, adcb15=1 mea ns data is negative value. note3: the positive full-scale-output value of adc conversion is 0x7a12. note4: the negative full-scale-output value of adc conversion is 0x85ee, adc conversion data (2?s compliment, hexadecimal) decimal value 0x7a12 31250 ? ? 0x4000 16384 ? ? 0x1000 4096 ? ? 0x0002 2 0x0001 1 0x0000 0 0xffff -1 0xfffe -2 ? ? 0xf000 -4096 ? ? 0xc000 -16384 ? ? 0x85ee -31250
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 118 preliminary version 1.2 10.5.5 dfm-adc digital filter mode register 097h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dfm - - - - - wrs0 - drdy - - - - - r/w - r/w bit0: drdy: adc data ready bit. 1 = adc output (update) new conversion data to adcd h, adcdl. 0 = adcdh, adcdl conversion data are not ready. bit2: wrs [1:0]: adc output word rate selection: output word rate wrs0 adc clock = 200k adc clock = 100k adc clock = 80k 0 50hz 25 hz 20 hz 1 25hz 12.5 hz 10 hz note 1: ac power 50 hz noise will be filter out whe n output word rate = 25hz note 2: ac power 60 hz noise will be filter out whe n output word rate = 20hz note 3: both ac power 50 hz and 60 hz noise will be filter out when output word rate = 10hz note 4: clear bit drdy after got adc data or this b it will keep high all the time. note 5: adjust adc clock (adcks) and bit wrs0 can g et suitable adc output word rate.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 119 preliminary version 1.2 10.5.6 analog setting and application the most applications of SN8P1989 were for dc measu rement in different applications had each analog ca pacitor setting to avoid vdd drop when charge pump enable o r can save cost. following table indicate different applications setting which mcu power source came from, aa/aaa dr y battery or external regulator resistance and capacitor table: ai+ ai- x+/x- ao+ /ao- r+/r- acm avddr ave+ avdd (pin17) vdd (pin21/38) power type c ai+ c ai- c x r ao+/ r ao- c r c acm c avddr c ave+ c avdd c dvdd aa/aaa bat.(4.4~5.5v) 0.1uf 0.1uf 0.1uf 100k 0.1uf 1uf 1uf 4.7uf 10uf 0.1uf/2.2uf external 5v reg. 0.1uf 0.1uf 0.1uf 100k 0.1uf 1uf 1uf 4.7uf 10uf 0.1uf/2.2uf note: the positive note of c acm connect to avddr and negative note connect to acm vdd=4.2v~5.5v analog capacitor connection delay time: power type enable acm enable avddr enable ave+ aa/aaa bat.(4.4~6v) 5ms 50ms 50ms external 5v reg. 5ms 50ms 50ms acm c acm avddr avddr ave+ c ave+ c avddr avss
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 120 preliminary version 1.2 10.5.7 lbtm : low battery detect register SN8P1989 provided two different way to measure powe r voltage. one is from adc reference voltage select ion. it will be more precise but take more time and a little bit complex. the another way is using build in voltage comparator, divide power voltage and connect to p5.2, bit lbto will output the p5.2 voltage higher or lower than a cm(1.2v) 09ah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lbtm - - - - - lbto - lbtenb r/w - - - - - r - r/w after reset - - - - - 0 - 0 bit0 lbtenb: low battery detect mode control bit. 0 = disable low battery detect function, 1 = enable low battery detect function bit2: lbto: low battery detect output bit. 0 = p52/lbt voltage higher than acm (1.2v) 1 = p52/lbt voltage lower than acm (1.2v) the lbt circuit will leak a small current in power down mode . these two circuit is following: lbtenb=1 comparator acm lbt vdd p5.2 r1 r2 vss 0.1u low battery voltage r1 r2 lbto=1 4.2v 2.5m 1m vdd<4.2v 4.8v 1.5m 0.5m vdd<4.8v note: get lbto=1 more 10 times in a raw every certa in period, ex. 20 ms or more to make sure the low battery signal is stable.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 121 preliminary version 1.2 1 1 1 1 1 1 2 channel analog to digital converter 11.1 overview this analog to digital converter has 2-input source s with up to 4096-step resolution to transfer analo g signal into 12-bits digital data. the sequence of adc operation is to s elect input source (ain0 ~ ain1) at first, then set gchs and ads bit to ?1? to start conversion. when the conversion is complete, the adc circuit will set eoc bit to ? 1? and final value output in adb register. this adc circuit can select between 8-bit and 12-bit resolution operation by p rogramming adlen bit in adr register. note: for 12-bit resolution the conversion time is 16 steps note: adc programming notice: 1. disable adc before enter power down (sleep) mode to save power consumption. 2. delay 100us after enable adc (set adenb = ?1?) t o wait adc circuit ready for conversion. 3. disable adc (set adenb = ?0?) before enter sleep mode to save power consumption. ain0 ain1 a/d converter (adc) data bus 12-bits
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 122 preliminary version 1.2 11.2 adc12m register 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc12m adc12enb ads eoc gchs - adc12chs2 adc12chs1 adc12chs0 read/write r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 7 adc12enb: adc control bit. 0 = disable. 1 = enable. bit 6 ads: adc start bit. 0 = stop. 1 = starting. bit 5 eoc: adc status bit. 0 = progressing. 1 = end of converting and reset ads bit. bit 4 gchs: global channel select bit. 0 = disable ain channel. 1 = enable ain channel. bit[2:0] adc12chs[2:0]: adc input channels select bit. adc12chs [2:0] selected channel 000 ain0 001 ain1 others reserved
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 123 preliminary version 1.2 11.3 adr registers 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - ad12cks1 - ad12cks0 adb3 adb2 adb1 adb0 read/write - r/w - r/w r r r r after reset - 0 - 0 - - - - bit 6,4 ad12cks [1:0]: adc?s clock source select bit. ad12cks1 ad12cks0 adc clock source adc clock source 0 0 fcpu/4 both validate in normal mode and slow mo de 0 1 fcpu/2 both validate in normal mode and slow mo de 1 0 fhosc only validate in normal mode 1 1 fhosc/2 only validate in normal mode bit [3:0] adb [3:0]: adc data buffer. adb11~adb4 bits for 8-bit adc adb11~adb0 bits for 12-bit adc note: adc buffer adr [3:0] initial value after rese t is unknown.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 124 preliminary version 1.2 11.4 adb registers 0b2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 read/write r r r r r r r r after reset - - - - - - - - bit[7:0] adb[11:4]: adc high-byte data buffer of 12-bit adc resolution. adb is adc data buffer to store ad converter result . the adb is only 8-bit register including bit 4~bi t11 adc data. to combine adb register and the low-nibble of adr will get full 12-bit adc data buffer. the adc buffer is a read-only register. in 12-bit adc mode, the adc data is store d in adb and adr registers. the ain?s input voltage v.s. adb?s output data ain n adb1 1 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 0/4096*vrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/4096*vrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/4096*vrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/4096*vrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more t han 8-bit resolution but less than 12-bit adc conve rter. to process the adb and adr data can make the job well. first, the ad resolution must be set 12-bit mode and then to execute adc converter routine. then delete the lsb of adc d ata and get the new resolution result. the table is as following. adb adr adc resolution adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8-bit o o o o o o o o x x x x 9-bit o o o o o o o o o x x x 10-bit o o o o o o o o o o x x 11-bit o o o o o o o o o o o x 12-bit o o o o o o o o o o o o o = selected, x = delete note: adc buffer adb initial value after reset is u nknown.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 125 preliminary version 1.2 11.5 adc converting time 12-bit adc conversion time = 1/(adc clock /4)*16 sec fcpu = 1mhz ( high clock, fosc is 4mhz and fcpu = f osc/4) adlen adcks1 adcks0 adc clock adc conversion time 0 0 fcpu/16 1/(1mhz/16/4)*16 = 1024 us 0 1 fcpu/8 1/(1mhz/8/4)*16 = 512 us 1 0 fcpu 1/(1mhz/4)*16 = 64 us 1 (12-bit) 1 1 fcpu/2 1/(1mhz/2/4)*16 = 128 us
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 126 preliminary version 1.2 11.6 adc routine example example : configure ain0 as 12-bit adc input and st art adc conversion then enter power down mode. adc0: b0bset fadenb ; enable adc circuit call delay100us ; delay 100us to wait adc circuit ready for conversion mov a, #60h b0mov adr, a ; to set 12-bit adc and adc clock = f osc. mov a,#90h b0mov adc12m,a ; to enable adc and set ain0 input b0bset fads ; to start conversion wadc0: b0bts1 feoc ; to skip, if end of converting =1 jmp wadc0 ; else, jump to wadc0 b0mov a,adb ; to get ain0 input data bit11 ~ bit4 b0mov adc_buf_hi, a b0mov a,adr ; to get ain0 input data bit3 ~ bit0 and a, 0fh b0mov adc_buf_low, a power_down . . b0bclr fadenb ; disable adc circuit b0bclr fcpum1 b0bset fcpum0 ; enter sleep mode
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 127 preliminary version 1.2 11.7 adc circuit adc reference high voltage is from vdd pin. mcu vcc gnd ainn v d d vss 0.1uf analog signal input 47uf 0.1uf
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 128 preliminary version 1.2 1 1 1 2 2 2 instruction table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bnak 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, (m = only for working registers r, y, z , rbank & pflag) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 mul a,m r, a a * m, the lb of product stored in acc and hb store d in r register. zf affected by acc. - - 2 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next ins truction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next ins truction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 129 preliminary version 1.2 s push to push working registers (080h~087h) into b uffers - - - 1 c pop to pop working registers (080h~087h) from buf fers 1 nop no operation - - - 1 note: 1. processing oscm register needs to add extra one c ycle. 2. if branch condition is true then ?s = 1?, otherwi se ?s = 0?.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 130 preliminary version 1.2 1 1 1 3 3 3 electrical characteristic 13.1 absolute maximum rating supply voltage (v dd )??? ???????????..????????????? - 0.3v ~ 6.0v input in voltage (v in )???????????..???.???????? v ss - 0.2v ~ v dd + 0.2v operating ambient temperature (t opr )??????????????????? 0 c ~ + 70 c storage ambient temperature (t stor )???????..???.???????? ?40 c ~ + 125 c 13.2 electrical characteristic (all of voltages refer to v ss , v dd = 5.0v,f osc = 4mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit operating voltage v dd normal mode, v pp = v dd 4.2 5.0 5.5 v ram data retention voltage v dr 1.5 - v v dd rise rate v por v dd rise rate to ensure power-on reset 0.05 - - v/ms vil1 all input ports vss - 0.3vdd v input low voltage vil2 reset pin vss - 0.2vdd v vih1 all input ports 0.7vdd - vdd v input high voltage vih2 reset pin 0.9vdd - vdd v reset pin leakage current i lekg v in = v dd - - 2 ua v in = v ss , v dd = 3v 100 200 300 k i/o port pull-up resistor r up v in = v ss , v dd = 5v 50 100 180 k i/o port input leakage current i lekg pull-up resistor disable, v in = v dd - - 2 ua i/o output source current i o h v op = v dd - 0.5v 9 - - ma sink current i o l v op = v ss + 0.5v 10 - - ma int n trigger pulse width t int 0 int0 ~ int1 interrupt request pulse width 2/f cpu - - cycle avrefh input voltage varfh vdd = 5.0v 2v - vdd v ain0 ~ ain1 input voltage vani vdd = 5.0v 0 - varfh v 12-bit adc current consumption i adc vdd=5.0v - 0.6* - ma 12-bit adc enable time tast ready to start convert after set adenb = ?1? 100 - - us 12-bit adc clock frequency f adclk vdd=5.0v 32k 8m hz 12-bit adc conversion cycle time f adcyl vdd=2.4v~5.5v 64 1/f adc lk 12-bit adc sampling rate (set fads=1 frequency) f adsmp vdd=5.0v 125 k/sec 12-bit adc differential nonlinearity dnl vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 1 2 4 lsb 12-bit adc integral nonlinearity inl vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 2 4 8 lsb 12-bit adc no missing code nmc vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 10 bits idd1 normal mode ( analog parts off) vdd= 5v 4mhz crystal - 1.5 3 ma idd4 normal mode (analog parts on) vdd= 5v 4mhz crystal - 2.5 4 ma supply current idd9 slow mode (stop high clock, lcd off, reg off) vdd= 5v ilrc 32khz - 10 20 ua
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 131 preliminary version 1.2 idd10 slow mode (stop high clock, lcd on, reg off) vdd= 5v ilrc 32khz - 25 50 ua idd11 slow mode (stop high clock, lcd on, reg on) vdd= 5v ilrc 32khz - 300 600 ua vdd= 5v - 1 2 ua idd12 sleep mode vdd= 3v - 0.7 1.5 ua lvd detect level v lvd internal por detect level 2.1 2.4 2.6 v *these parameters are for design reference, not tes ted. note: analog parts including regulator (reg), pgia and adc.
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 132 preliminary version 1.2 (all of voltages refer to vdd=3.8v f osc = 4mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit 16-bit analog to digital converter operating current i dd_adc run mode @ 3.8v 800 1000 ua power down current i pdn stop mode @ 3.8v 0.1 1 a conversion rate f smp adcks: 200khz 25 sps reference voltage input voltage vref r+, r- input voltage 0.4 2.0 v differential non-linearity dnl 0.5 0.5 lsb integral non-linearity inl 1 4 lsb no missing code nmc 16 bit noise free code nfc 14 16 bit effective number of bits enob 14 16 bit adc input range v ain 0.4 2.0 v pgia current consumption i dd_pgia run mode @ 3.8v 300 500 ua power down current i pdn stop mode @ 3.8v 0.1 a input offset voltage vos 2 uv bandwidth bw 100 hz pgia gain range (gain=200x) gr vdd = 3.8v 180 200 250 pgia input range vopin vdd = 3.8v 0.4 2 v pgia output range vopout vdd = 3.8v 0.4 2 v band gap reference (refer to acm) band gap reference voltage v bg 1.150 1.220 1.250 v reference voltage temperature coefficient t acm 50* ppm/ operating current i bg run mode @ 3.8v 50 100 ua regulator supply voltage v cps normal mode 2.4 5.5 v regulator output voltage avddr v cpo1 3.70 3.8 3.95 v regulator output voltage ave+ v cpo2 2.95 3.1 3.15 v analog common voltage v acm 1.19 1.22 1.25 v regulator output current capacity i va+ 10 ma quiescent current i qi - 700 1400 ua v acm driving capacity i src - - 10 a v acm sinking capacity i snk - - 1 ma
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 133 preliminary version 1.2 1 1 1 4 4 4 package information 14.1 lqfp80
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 134 preliminary version 1.2 1 1 1 5 5 5 marking definition 15.1 introduction there are many different types in sonix 8-bit mcu p roduction line. this note listed the production def inition of all 8-bit mcu for order or obtain information. this definitio n is only for blank otp mcu. 15.2 marking indetification system sn8 x part no. x x x title sonix 8-bit mcu production rom type p=otp material b = pb-free package g = green package temperature range - = 0 ~ 70 shipping package device
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 135 preliminary version 1.2 15.3 marking example name rom type device package temperature material SN8P1989fg otp 1989 lqfp 0 ~70 green package SN8P1989fb otp 1989 lqfp 0 ~70 pb-free package 15.4 datecode system there are total 8~9 letters of sonix datecode syste m. the final four or five char. are for sonix insid e use only, and the first 4 indicate the package date including year/mo nth/date. the detail information is following: x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 136 preliminary version 1.2 1 1 1 6 6 6 programming pin 16.1 writer pin assignment jp3 (mapping to 48-pin text tool) writer jp1/jp2 dip 1 1 48 dip48 vdd 1 2 vss dip 2 2 47 dip47 clk 3 4 ce dip 3 3 46 dip46 pgm 5 6 oe dip 4 4 45 dip45 d1 7 8 d0 dip 5 5 44 dip44 d3 9 10 d2 dip 6 6 43 dip43 d5 11 12 d4 dip 7 7 42 dip42 d7 13 14 d6 dip 8 8 41 dip41 vdd 15 16 vpp dip 9 9 40 dip40 hls 17 18 rst dip10 10 39 dip39 - 19 20 alsb/pdb dip11 11 38 dip38 dip12 12 37 dip37 jp1 for writer transition board dip13 13 36 dip36 jp2 for dice and >48 pin package dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 25 dip25
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 137 preliminary version 1.2 16.2 programming pin mapping: programming pin information of SN8P1989 series chip name SN8P1989(lqfp) writer connector ic pin assignment jp1/jp2 pin number jp1/jp2 pin name ic pin number ic pin name 1 vdd 18/35/80/55/50 vdd/vlcd/vlcd1/vlcd2 2 gnd 23/45/11 vss/avss 3 clk 27 p10 4 ce - - 5 pgm 28 p11 6 oe 29 p12 7 d1 - - 8 d0 - - 9 d3 - - 10 d2 - - 11 d5 - - 12 d4 - - 13 d7 - - 14 d6 - - 15 vdd 18/35/80/55/50 vdd/avdd/vlcd/vlcd1/vlcd2 16 vpp 24 vpp/rst 17 hls - - 18 rst - - 19 - - - 20 alsb/pdb 30 p13
SN8P1989 8-bit micro-controller with regulator, pgia, 16-bit adc sonix technology co., ltd page 138 preliminary version 1.2 sonix reserves the right to make change without furt her notice to any products herein to improve reliab ility, function or design. sonix does not assume any liability arising out of the application or use of any product or cir cuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in sys tems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any oth er application in which the failure of the sonix pro duct could create a situation where personal injury or death may occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employe es, subsidiaries, affiliates and distributors harmless against all cl aims, cost, damages, and expenses, and reasonable a ttorney fees arising out of, directly or indirectly, any claim of person al injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 10f-1, no.36, taiyuan street, chupei city, hsinchu, taiwan. tel: 886-3-5600 888 fax: 886-3-5600 889 taipei office: address: 15f-2, no. 171, song ted road, taipei, tai wan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 granville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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